Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
211
32072H–AVR32–10/2012
AT32UC3A3
15.6.9.3
Page mode restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
the NWAIT signal may lead to unpredictable behavior.
15.6.9.4
Sequential and non-sequential accesses
If the chip select and the MSB of addresses as defined in
are identical,
then the current access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (t
with a minimum access time (t
sa
).
illustrates access to an 8-bit mem-
ory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long
access time (t
access time (t
pa
). Accesses to D3 and D7, though they are not sequential accesses, only require
a short access time (t
sa
).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
Figure 15-34. Access to Non-sequential Data within the Same Page
CLK_SMC
A[AD_MSB:3]
A[2], A1, A0
NCS
NRD
D[7:0]
A1
Page address
A3
A7
D1
D3
D7
NCSRDPULSE
NRDPULSE
NRDPULSE