Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
225
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-4. Write Burst, 16-bit SDRAM Access
16.7.3
SDRAM Controller Read Cycle
The SDRAMC allows burst access, incremental burst of unspecified length or single access. In
all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing perfor-
mance of the SDRAM. If row and bank addresses do not match the previous row/bank address,
then the SDRAMC automatically generates a precharge command, activates the new row and
starts the read command. To comply with the SDRAM timing parameters, additional clock cycles
on SDCK are inserted between precharge and active (t
all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing perfor-
mance of the SDRAM. If row and bank addresses do not match the previous row/bank address,
then the SDRAMC automatically generates a precharge command, activates the new row and
starts the read command. To comply with the SDRAM timing parameters, additional clock cycles
on SDCK are inserted between precharge and active (t
RP
) commands and between active and
read (t
RCD
) commands. These two parameters are set in the CR register of the SDRAMC. After a
read command, additional wait states are generated to comply with the CAS latency (one, two,
or three clock delays specified in the CR register).
or three clock delays specified in the CR register).
For a single access or an incremented burst of unspecified length, the SDRAMC anticipates the
next access. While the last value of the column is returned by the SDRAMC on the bus, the
SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This
reduces the effect of the CAS latency on the internal bus.
next access. While the last value of the column is returned by the SDRAMC on the bus, the
SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This
reduces the effect of the CAS latency on the internal bus.
For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads
to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han-
dled as an incrementing burst of unspecified length.
to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han-
dled as an incrementing burst of unspecified length.
SDCS
t
RCD
= 3
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDWE
D[15:0]
Dna
Dnb
Dnc
Dnd
Dne
Dnf
Dng
Dnh
Dni
Dnj
Dnk
Dnl
Row n
Col b
Col c
Col d Col e
Col f
Col g
Col h Col i
Col k
Col l
Col j
Col a