Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
226
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-5. Read Burst, 16-bit SDRAM Access
16.7.4
Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAMC generates a precharge command, activates the new row and initiates a read
or write command. To comply with SDRAM timing parameters, an additional clock cycle is
inserted between the precharge and active (t
case, the SDRAMC generates a precharge command, activates the new row and initiates a read
or write command. To comply with SDRAM timing parameters, an additional clock cycle is
inserted between the precharge and active (t
RP
) commands and between the active and read
(t
RCD
) commands. This is described in
.
SDCS
D[15:0]
(Input)
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDWE
Dna
Dnb
Dnc
Dnd
Dne
Dnf
Col a
Col b
Col c
Col d
Col e
Col f
Row n
CAS = 2
t
RCD
= 3