Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Figure 16-7. Refresh Cycle Followed by a Read Access

Three low power modes are available:

• Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the 

SDRAMC. Current drained by the SDRAM is very low.

• Power-down mode: auto refresh cycles are controlled by the SDRAMC. Between auto refresh 

cycles, the SDRAM is in power-down. Current drained in power-down mode is higher than in 
self refresh mode.

• Deep power-down mode (only available with mobile SDRAM): the SDRAM contents are lost, 

but the SDRAM does not drain any current.

The SDRAMC activates one low power mode as soon as the SDRAM device is not selected. It is
possible to delay the entry in self refresh and power-down mode after the last access by config-
uring the Timeout field in the Low Power Register (LPR.TIMEOUT).

This mode is selected by writing the value one to the Low Power Configuration Bits field in the
SDRAMC Low Power Register (LPR.LPCB). In self refresh mode, the SDRAM device retains
data without external clocking and provides its own internal clocking, thus performing its own
auto refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE,
which remains low. As soon as the SDRAM device is selected, the SDRAMC provides a
sequence of commands and exits self refresh mode. 

Some low power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter
or all banks of the SDRAM array. This feature reduces the self refresh current. To configure this
feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR)

SDCS

SDCK

SDRAMC_A[12:0]

Row n

Col c Col d

RAS

CAS

SDWE

D[15:0]

(input)

Dnb

Dnc

Dnd

Dma

Col a

Row m

CAS = 2

t

RCD

 = 3

t

RC

 = 8

t

RP

 = 3