Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
23
32072H–AVR32–10/2012
AT32UC3A3
Figure 4-1.
Overview of the AVR32UC CPU
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
High
Speed
Bus
master
MPU
H
igh S
pee
d
Bu
s
H
igh S
pee
d
Bu
s
OCD
system
OC
D
in
te
rfa
ce
In
te
rru
pt c
on
tro
lle
r i
nte
rfa
ce
High
Speed
Bus slave
H
igh S
pee
d
Bu
s
Da
ta
RA
M
in
te
rfa
ce
High Speed Bus master
Power/
Reset
control
Re
se
t i
nt
er
fa
ce
CPU Local
Bus
master
CPU L
oc
al
B
us
Data memory controller