Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
25
32072H–AVR32–10/2012
AT32UC3A3
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
instructions require aligned addresses.
4.3.6
Unimplemented Instructions
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
Instruction Exception if executed:
• All SIMD instructions
• All coprocessor instructions if no coprocessors are present
• retj, incjosp, popjc, pushjc
• tlbr, tlbs, tlbw
• cache
4.3.7
CPU and Architecture Revision
Three major revisions of the AVR32UC CPU currently exist.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled
for revision 1 or 2 is binary-compatible with revision 3 CPUs.
for revision 1 or 2 is binary-compatible with revision 3 CPUs.
Table 4-1.
Instructions with Unaligned Reference Support
Instruction
Supported alignment
ld.d
Word
st.d
Word