Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

slave to pull it down in order to generate the acknowledge. The master polls the data line during
this clock pulse.

The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also
used as Receive Ready for the Peripheral DMA Controller receive channel.

Figure 22-10. Slave Receiver with One Data Byte

Figure 22-11. Slave Receiver with Multiple Data Bytes

The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set
up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space
to place received data. By initializing NBYTES to zero before a transfer, and writing a one to
CR.CUP, NBYTES is incremented by one each time a data has been transmitted or received.
This allows the user to detect how much data was actually transferred by the DMA system.

To assure correct behavior, respect the following programming sequences:

1.

Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).

2.

Configure the TWIS (ADR, NBYTES, etc.).

3.

Start the transfer by enabling the Peripheral DMA Controller to transmit.

4.

Wait for the Peripheral DMA Controller end-of-transmit flag.

5.

Disable the Peripheral DMA Controller.

1.

Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.).

2.

Configure the TWIS (ADR, NBYTES, etc.).

A

S

DADR

W

DATA

A

P

TCOMP

RXRDY

Read RHR

TWD

A

A

S

DADR

W

DATA  n

A

A

DATA (n+1)

A

DATA (n+m)

DATA (n+m)-1

P

TWD

TCOMP

RXRDY

Read RHR

DATA n

Read RHR

DATA (n+1)

Read RHR

DATA (n+m)-1

Read RHR

DATA (n+m)