Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
455
32072H–AVR32–10/2012
AT32UC3A3
22.8.7
Identifying Bus Events
This chapter lists the different bus events, and how these affects the bits in the TWIS registers.
This is intended to help writing drivers for the TWIS.
This is intended to help writing drivers for the TWIS.
Table 22-5.
Bus Events
Event
Effect
Slave transmitter has sent a
data byte
data byte
SR.THR is cleared.
SR.BTF is set.
The value of the ACK bit sent immediately after the data byte is given
by CR.ACK.
by CR.ACK.
Slave receiver has received
a data byte
a data byte
SR.RHR is set.
SR.BTF is set.
SR.NAK updated according to value of ACK bit received from master.
Start+Sadr on bus, but
address is to another slave
address is to another slave
None.
Start+Sadr on bus, current
slave is addressed, but
address match enable bit in
CR is not set
slave is addressed, but
address match enable bit in
CR is not set
None.
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set
slave is addressed,
corresponding address
match enable bit in CR set
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction (updating is done one
CLK_TWIS cycle after address match bit is set)
CLK_TWIS cycle after address match bit is set)
Slave enters appropriate transfer direction mode and data transfer
can commence.
can commence.
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set,
slave is addressed,
corresponding address
match enable bit in CR set,
SR.STREN and SR.SOAM
are set.
are set.
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction (updating is done one
CLK_TWIS cycle after address match bit is set).
CLK_TWIS cycle after address match bit is set).
Slave stretches TWCK immediately after transmitting the address
ACK bit. TWCK remains stretched until all address match bits in SR
have been cleared.
ACK bit. TWCK remains stretched until all address match bits in SR
have been cleared.
Slave enters appropriate transfer direction mode and data transfer
can commence.
can commence.
Repeated Start received
after being addressed
after being addressed
SR.REP set.
SR.TCOMP unchanged.
Stop received after being
addressed
addressed
SR.STO set.
SR.TCOMP set.
Start, Repeated Start, or
Stop received in illegal
position on bus
Stop received in illegal
position on bus
SR.BUSERR set.
SR.STO and SR.TCOMP may or may not be set depending on the
exact position of an illegal stop.
exact position of an illegal stop.
Data is to be received in
slave receiver mode,
SR.STREN is set, and RHR
is full
slave receiver mode,
SR.STREN is set, and RHR
is full
TWCK is stretched until RHR has been read.
Data is to be transmitted in
slave receiver mode,
SR.STREN is set, and THR
is empty
slave receiver mode,
SR.STREN is set, and THR
is empty
TWCK is stretched until THR has been written.