Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
can optionally be divided by any even integer up to 512. Each clock can be independently
enabled and disabled, and is also automatically disabled along with peripheral clocks by the
Sleep Controller.

Generic Clock Generation

A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
resulting in the output frequency:

The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables
the PB clocks. In either case, the generic clock will be switched off on the first falling edge after
the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as
1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0,
the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the
generic clock.

When the clock is disabled, both the prescaler and output are reset.

When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.

Divider

0

1

Osc0 clock

PLL0 clock

PLLSEL

OSCSEL

Osc1 clock

PLL1 clock

Generic Clock

DIV

0

1

DIVEN

Mask

CEN

Sleep 

Controller

2

1

+

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×

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