Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
51
32072H–AVR32–10/2012
AT32UC3A3
7.5.8.4
Generic clock implementation
The generic clocks are allocated to different functions as shown in
.
7.5.9
Divided PB Clocks
The clock generator in the Power Manager provides divided PBA and PBB clocks for use by
peripherals that require a prescaled PBx clock. This is described in the documentation for the
relevant modules.
peripherals that require a prescaled PBx clock. This is described in the documentation for the
relevant modules.
The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx
clocks are stopped.
clocks are stopped.
7.5.10
Debug Operation
The OCD clock must never be switched off if the user wishes to debug the device with a JTAG
debugger.
debugger.
During a debug session, the user may need to halt the system to inspect memory and CPU reg-
isters. The clocks normally keep running during this debug operation, but some peripherals may
require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program
to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx
clocks. This is described in the documentation for the relevant modules. The divided PBx clocks
are always debug qualified clocks.
isters. The clocks normally keep running during this debug operation, but some peripherals may
require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program
to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx
clocks. This is described in the documentation for the relevant modules. The divided PBx clocks
are always debug qualified clocks.
Debug qualified PBx clocks are stopped during debug operation. The debug system can option-
ally keep these clocks running during the debug operation. This is described in the
documentation for the On-Chip Debug system.
ally keep these clocks running during the debug operation. This is described in the
documentation for the On-Chip Debug system.
7.5.11
Reset Controller
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
soft resets for the digital logic.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be driven externally when negated.
lup, and does not need to be driven externally when negated.
lists these
and other reset sources supported by the Reset Controller.
Table 7-2.
Generic Clock Allocation
Clock number
Function
0
GCLK0 pin
1
GCLK1 pin
2
GCLK2 pin
3
GCLK3 pin
4
GCLK_USBB
5
GCLK_ABDAC