Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR
(TCMR.CKI).

The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actual data
transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register
(TCMR.CKO). The TCMR.CKI bit has no effect on the clock outputs.

Writing 0b10 to the TCMR.CKS field to select TX_CLOCK pin and 0b001 to the TCMR.CKO field
to select Continuous Transmit Clock can lead to unpredictable results.

Figure 24-6. Transmitter Clock Management

The receiver clock is generated from the transmitter clock, the divider clock, or an external clock
scanned on the RX_CLOCK pin. The receive clock is selected by writing to the Receive Clock
Selection field in the Receive Clock Mode Register (RCMR.CKS). The receive clock can be
inverted independently by writing a one to the Receive Clock Inversion bit in RCMR
(RCMR.CKI).

The receiver can also drive the RX_CLOCK pin continuously or be limited to the actual data
transfer, depending on the Receive Clock Output Mode Selection field in the RCMR register
(RCMR.CKO). The RCMR.CKI bit has no effect on the clock outputs.

Writing 0b10 to the RCMR.CKS field to select RX_CLOCK pin and 0b001 to the RCMR.CKO
field to select Continuous Receive Clock can lead to unpredictable results.

TX_CLOCK

Receiver

Clock

Divider

Clock

CKO

Data Transfer

Tri-state

Controller

INV

MUX

CKS

MUX

Tri-state

Controller

CKI

CKG

Transmitter

Clock

Clock

Output