Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Figure 24-8. Transmitter Block Diagram

A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.

The start event is configured by writing to the RCMR register. See 

The frame synchronization is configured by writing to the Receive Frame Mode Register
(RFMR). See 

.

The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR register. The data is transferred from the shift register depending on the
data format selected.

When the receiver shift register is full, the SSC transfers this data in the Receive Holding Regis-
ter (RHR), the Receive Ready bit is set in the SR register (SR.RXREADY) and the data can be
read in the RHR register. If another transfer occurs before a read of the RHR 

register

, the

Receive Overrun bit is set in the SR register (SR.OVRUN) and the receiver shift register is trans-
ferred to the RHR register.

TFMR.DATDEF

TFMR.MSBF

0

1

Transmit Shift Register

0

1

THR

TSHR

TFMR.FSLEN

TCMR.STTDLY

TFMR.FSDEN

TFMR.DATNB

CR.TXEN

CR.TXDIS

SR.TXEN

TX_DATA

TFMR.DATLEN

TCMR.STTDLY

TFMR.FSDEN

Start

Selector

RX_FRAME_SYNC

TX_FRAME_SYNC

Transmitter Clock