Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
526
32072H–AVR32–10/2012
AT32UC3A3
24.9.2
Clock Mode Register
Name:
CMR
Access Type:
Read/Write
Offset:
0x04
Reset value:
0x00000000
• DIV[11:0]: Clock Divider
The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is
CLK_SSC/(2 x 4095) = CLK_SSC/8190.
The clock divider is not active when DIV equals zero.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
DIV[11:8]
7
6
5
4
3
2
1
0
DIV[7:0]
Divided Clock
CLK_SSC (
⁄ DIV
2)
×
=