Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
527
32072H–AVR32–10/2012
AT32UC3A3
24.9.3
Receive Clock Mode Register
Name:
RCMR
Access Type:
Read/Write
Offset:
0x10
Reset value:
0x00000000
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods.
• STTDLY: Receive Start Delay
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.
Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be done in relation to Receive
Sync Data reception.
• STOP: Receive Stop Selection
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new
Compare 0.
31
30
29
28
27
26
25
24
PERIOD
23
22
21
20
19
18
17
16
STTDLY
15
14
13
12
11
10
9
8
-
-
-
STOP
START
7
6
5
4
3
2
1
0
CKG
CKI
CKO
CKS