Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
57
32072H–AVR32–10/2012
AT32UC3A3
7.6.2
Clock Select Register
Name: CKSEL
Access Type:
Read/Write
Offset:
0x04
Reset Value:
0x00000000
• PBBDIV: PBB Division Enable
PBBDIV = 0: PBB clock equals main clock.
PBBDIV = 1: PBB clock equals main clock divided by 2
(PBBSEL+1)
.
• PBADIV, PBASEL: PBA Division and Clock Select
PBADIV = 0: PBA clock equals main clock.
PBADIV = 1: PBA clock equals main clock divided by 2
(PBASEL+1)
.
• CPUDIV, CPUSEL: CPU/HSB Division and Clock Select
CPUDIV = 0: CPU/HSB clock equals main clock.
CPUDIV = 1: CPU/HSB clock equals main clock divided by 2
(CPUSEL+1)
.
Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation.
Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high.
31
30
29
28
27
26
25
24
PBBDIV
-
-
-
-
PBBSEL
23
22
21
20
19
18
17
16
PBADIV
-
-
-
-
PBASEL
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
CPUDIV
-
-
-
-
CPUSEL