Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
58
32072H–AVR32–10/2012
AT32UC3A3
7.6.3
Clock Mask Registers
Name: CPU/HSB/PBA/PBBMASK
Access Type:
Read/Write
Offset:
0x08-0x14
Reset Value:
0x00000003/0x00000FFF/0x001FFFFF/0x000003FF
• MASK: Clock Mask
If bit n is written to zero, the clock for module n is stopped. If bit n is writen to one, the clock for module n is enabled according to
the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by
each bit, is shown in
.
31
30
29
28
27
26
25
24
MASK[31:24]
23
22
21
20
19
18
17
16
MASK[23:16]
15
14
13
12
11
10
9
8
MASK[15:8]
7
6
5
4
3
2
1
0
MASK[7:0]
Table 7-7.
Maskable module clocks in AT32UC3A3.
Bit
CPUMASK
HSBMASK
PBAMASK
PBBMASK
0
-
FLASHC
INTC
HMATRIX
1
OCD
PBA Bridge
I/O
USBB
2
-
PBB Bridge
PDCA
FLASHC
3
-
USBB
PM/RTC/EIC
SMC
4
-
PDCA
ADC
SDRAMC
5
-
EBI
SPI0
ECCHRS
6
-
PBC Bridge
SPI1
MCI
7
-
DMACA
TWIM0
BUSMON
8
-
BUSMON
TWIM1
MSI
9
-
HRAMC0
TWIS0
AES
10
-
HRAMC1
TWIS1
-
11
-
USART0
-
12
-
-
USART1
-
13
-
-
USART2
-
14
-
-
USART3
-
15
-
-
SSC
-