Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

LINMR

Read-write

0x54

0x00000000 

0: The LIN mode register is not written by the Peripheral DMA Controller.

1: The LIN mode register, except for this bit, is written by the Peripheral DMA Controller.

0 - 255: If DLM=0 this field defines the response data length to DLC+1 bytes.

0: Writing a one to CR.LINWKUP will send a LIN 2.0 wakeup signal.

1: Writing a one to CR.LINWKUP will send a LIN 1.3 wakeup signal.

0: The Frame Slot mode is enabled.

1: The Frame Slot mode is disabled.

0: The response data length is defined by DLC.

1: The response data length is defined by bits 4 and 5 of the Identifier (LINIR.IDCHR).

0: LIN 2.0 “Enhanced” checksum

1: LIN 1.3 “Classic” checksum

0: Checksum is automatically computed and sent when master, and checked when slave.

1: Checksum is not computed and sent, nor checked.

0: Identifier parity is automatically computed and sent when master, and checked when slave.

1: Identifier parity is not computed and sent, nor checked.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

PDCM

15

14

13

12

11

10

9

8

DLC

7

6

5

4

3

2

1

0

WKUPTYP

FSDIS

DLM

CHKTYP

CHKDIS

PARDIS

NACT

0

0

PUBLISH: The USART transmits the response.