Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

In device mode, the USBB supports hi- full- and low-speed data transfers.

In addition to the default control endpoint, seven endpoints are provided, which can be config-
ured with the types isochronous, bulk or interrupt, as described in .

.

The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.

 describes the USBB device mode main states.

Figure 27-12. Device Mode States

After a hardware reset, the USBB device mode is in the Reset state. In this state:

• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to 

one).

• The internal registers of the device mode are reset.

• The endpoint banks are de-allocated.

• Neither D+ nor D- is pulled up (DETACH is written to one).

D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is present. See 

 for further details.

When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.

The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).

The USB bus reset is managed by hardware. It is initiated by a connected host.

When a USB reset is detected on the USB line, the following operations are performed by the
controller:

• All the endpoints are disabled, except the default control endpoint.

Reset

Idle

   HW
RESET

  USBE = 0
| ID = 0

  USBE = 0
| ID = 0

   USBE = 1
& ID = 1