Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP)
interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power con-
sumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power
consumption.

To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit,
which is set when a non-idle event is detected, then write a zero to FRZCLK.

As the WAKEUP interrupt bit in UDINT is set when a non-idle event is detected, it can occur
whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are
thus independent of each other except that one bit is cleared when the other is set.

The reset value of the DETACH bit is one.

It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH.

DETACH acts on the pull-up connections of the D+ and D- pads. See 

 for further

details.

The Remote Wake-Up request (also known as Upstream Resume) is the only one the device
may send on its own initiative, but the device should have beforehand been allowed to by a
DEVICE_REMOTE_WAKEUP request from the host.

• First, the USBB must have detected a “Suspend” state on the bus, i.e. the Remote Wake-Up 

request can only be sent after a SUSP interrupt has been set.

• The user may then write a one to the Remote Wake-Up (RMWKUP) bit in UDCON to send an 

upstream resume to the host for a remote wake-up. This will automatically be done by the 
controller after 5ms of inactivity on the USB bus.

• When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt 

is set and SUSP is cleared.

• RMWKUP is cleared at the end of the upstream resume.

• If the controller detects a valid “End of Resume” signal from the host, the End of Resume 

(EORSM) interrupt is set.

For each endpoint, the STALL management is performed using:

• The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request.

• The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been 

sent.

To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one
to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI,
etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is
done when a new SETUP packet is received (for control endpoints) or when the STALL Request
Clear (STALLRQC) bit is written to one.

Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT
interrupt is set.