Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
712
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.18
Device DMA Channel n HSB Address Register
Register Name:
UDDMAnADDR, n in [1..7]
Access Type:
Read/Write
Offset:
0x0314 + (n - 1) * 0x10
Reset Value:
0x00000000
• HSBADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,
HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access
byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the
end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.
31
30
29
28
27
26
25
24
HSBADDR[31:24]
23
22
21
20
19
18
17
16
HSBADDR[23:16]
15
14
13
12
11
10
9
8
HSBADDR[15:8]
7
6
5
4
3
2
1
0
HSBADDR[7:0]