Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

Product codes
AT32UC3A3-XPLD
Page of 1021
713
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.19
Device DMA Channel n Control Register
Register Name:
UDDMAnCONTROL, n in [1..7]
Access Type:
Read/Write
Offset:
0x0318 + (n - 1) * 0x10
Reset Value:
0x00000000
• CHBYTELENGTH: Channel Byte Length
This field determines the total number of bytes to be transferred for this buffer.
The maximum channel transfer size 64kB is reached when this field is zero (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.
This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is 
ignored.
• BURSTLOCKEN: Burst Lock Enable
1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.
0: The DMA never locks the HSB access.
• DESCLDIRQEN: Descriptor Loaded Interrupt Enable
1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system 
bus.
0: The Descriptor Loaded interrupt is disabled.
• EOBUFFIRQEN: End of Buffer Interrupt Enable
1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.
0: The end of buffer interrupt is disabled.
• EOTIRQEN: End of USB Transfer Interrupt Enable
1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.
0: The end of usb OUT data transfer interrupt is disabled.
• DMAENDEN: End of DMA Buffer Output Enable
Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (but not a Zero Length Packet) will be sent to the USB line to properly closed the 
usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
31
30
29
28
27
26
25
24
CHBYTELENGTH[15:8]
23
22
21
20
19
18
17
16
CHBYTELENGTH[7:0]
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
BURSTLOCKEN
DESCLDIRQEN
EOBUFFIRQEN
EOTIRQEN
DMAENDEN
BUFFCLOSE
INEN
LDNXTCH
DESCEN
CHEN