Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
715
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.20
Device DMA Channel n Status Register
Register Name:
UDDMAnSTATUS, n in [1..7]
Access Type:
Read/Write
Offset:
0x031C + (n - 1) * 0x10
Reset Value:
0x00000000
• CHBYTECNT: Channel Byte Count
This field contains the current number of bytes still to be transferred for this buffer.
This field is decremented at each dma access.
This field is reliable (stable) only if the CHEN bit is zero.
• DESCLDSTA: Descriptor Loaded Status
This bit is set when a Descriptor has been loaded from the HSB bus.
This bit is cleared when read by the user.
• EOCHBUFFSTA: End of Channel Buffer Status
This bit is set when the Channel Byte Count counts down to zero.
This bit is automatically cleared when read by software.
• EOTSTA: End of USB Transfer Status
This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if
UDDMAnCONTROL.BUFFCLOSEINEN is one. Note that for OUT endpoint, if the UECFGn.AUTOSW is set, any received zero-
length-packet will be cancelled by the DMA, and the EOTSTA will be set whatever the UDDMAnCONTROL.CHEN bit is.
This bit is automatically cleared when read by software.
• CHACTIVE: Channel Active
0: the DMA channel is no longer trying to source the packet data.
1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a
packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if any)
and potentially until USB packet transfer completion, if allowed by the new descriptor.
When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running
(the endpoint is free for IN transaction, the endpoint is full for OUT transaction).
• CHEN: Channel Enabled
This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded.
This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end.
31
30
29
28
27
26
25
24
CHBYTECNT[15:8]
23
22
21
20
19
18
17
16
CHBYTECNT[7:0]
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
DESCLD
STA
EOCHBUFF
STA
EOTSTA
-
-
CHACTIVE
CHEN