Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
844
32072H–AVR32–10/2012
AT32UC3A3
31.7.2
Mode Register
Name: MR
Access Type: Read-write
Offset: 0x004
Reset Value:
0x00000000
• BLKLEN[15:0]: Data Block Length
This field determines the size of the data block.
This field is also accessible in the BLKR register.
If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00
Notes:
1. In SDIO Byte mode, BLKLEN field is not used.
2. BLKLEN should be written to one before sending the data transfer command. Otherwise,
2. BLKLEN should be written to one before sending the data transfer command. Otherwise,
Overrun may occur even if RDPROOF bit is one.
• PADV: Padding Value
0: 0x00 value is used when padding data in write transfer.
1: 0xFF value is used when padding data in write transfer.
PADV is used only in manual transfer.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allows byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
Writing a one to this bit will enable the Force Byte Transfer.
Writing a zero to this bit will disable the Force Byte Transfer.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the MCI Clock (CLK) during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Write Proof mode.
Writing a zero to this bit will disable the Write Proof mode.
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the MCI Clock (CLK) during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Read Proof mode.
Writing a zero to this bit will disable the Read Proof mode.
31
30
29
28
27
26
25
24
BLKLEN[15:8]
23
22
21
20
19
18
17
16
BLKLEN[7:0]
15
14
13
12
11
10
9
8
-
PADV
FBYTE
WRPROOF
RDPROOF
PWSDIV
7
6
5
4
3
2
1
0
CLKDIV