Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
863
32072H–AVR32–10/2012
AT32UC3A3
31.7.16
DMA Configuration Register
Name: DMA
Access Type: Read/Write
Offset: 0x050
Reset Value:
0x00000000
• DMAEN: DMA Hardware Handshaking Enable
1: DMA Interface is enabled.
0: DMA interface is disabled.
To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed.
To avoid data losses, the DMA register should be initialized before sending the data transfer command. This is also illustrated in
• CHKSIZE: DMA Channel Read and Write Chunk Size
The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted.
• OFFSET: DMA Write Buffer Offset
This field indicates the number of discarded bytes when the DMA writes the first word of the transfer.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
DAMEN
7
6
5
4
3
2
1
0
-
CHKSIZE
-
-
OFFSET
CHKSIZE value
Number of data transferred
0
1
Only available if FIFO_SIZE>= 16 bytes
1
4
Only available if FIFO_SIZE>= 32 bytes
2
8
Only available if FIFO_SIZE>= 64 bytes
3
16
Only available if FIFO_SIZE>= 128 bytes
4
32
Only available if FIFO_SIZE>= 256 bytes
others
-
Reserved