Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

Product codes

AT32UC3A3-XPLD

864

32072H–AVR32–10/2012

AT32UC3A3

31.7.17

Configuration Register

Name: CFG

Access Type: Read/Write

Offset: 0x054

Reset Value:

0x00000000

• LSYNC: Synchronize on the last block

1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be

different from zero)

0: The pending command is sent at the end of the current data block.

This register needs to configured before sending the data transfer command.

• HSMODE: High Speed Mode

1: The host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the

high speed support in the card registers.

0: Default bus timing mode.

• FERRCTRL: Flow Error bit reset control mode

1: When an underflow/overflow condition bit is set, reading SR resets the bit.

0: When an underflow/overflow condition bit is set, a new Write/Read command is needed to reset the bit.

• FIFOMODE: MCI Internal FIFO control mode

1: A write transfer starts as soon as one data is written into the FIFO.

0: A write transfer starts when a sufficient amount of data is written into the FIFO.

When the block length is greater than or equal to 3/4 of the MCI internal FIFO size, then the write transfer starts as soon as half

the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as

soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the

internal FIFO.

LSYNC

HSMODE

FERRCTRL

FIFOMODE