Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

• During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat 

scanning until the busy bit clears.

• During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat 

scanning until the busy bit clears.

The Service Access Bus may not be able to complete all accesses as requested. This may be
because the address is invalid, the addressed area is read-only or cannot handle byte/halfword
accesses, or because the chip is set in a protected mode where only limited accesses are
allowed.

The error bit is updated when an access completes, and is cleared when a new access starts.

What to do if the error bit is set:

• During Shift-IR: The new instruction is selected. The last operation performed using the old 

instruction did not complete successfully.

• During Shift-DR of an address: The previous operation failed. The new address is accepted. 

If the read bit is set, a read operation is started.

• During Shift-DR of read data: The read operation failed, and the read data is invalid.

• During Shift-DR of write data: The previous write operation failed. The new data is accepted 

and a write operation started. This should only occur during block writes or stream writes. No 
error can occur between scanning a write address and the following write data.

• While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not 

have actually completed.

• After power-up: The error bit is set after power up, but there has been no previous SAB 

instruction so this error can be discarded.

A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security
bit in the Flash Controller is set and that the chip is locked for access, according to 

The protected state is reported when:

• The Flash Controller is under reset. This can be due to the AVR_RESET command or the 

RESET_N line.

• The Flash Controller has not read the security bit from the flash yet (This will take a a few 

ms). Happens after the Flash Controller reset has been released.

• The security bit in the Flash Controller is set.

What to do if the protected bit is set:

• Release all active AVR_RESET domains, if any.

• Release the RESET_N line.

• Wait a few ms for the security bit to clear. It can be set temporarily due to a reset.

• Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the 

non-volatile memory.