Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
278
AT32UC3A
25.9.3
Receive Clock Mode Register
Name:
RCMR
Access Type:
Read/Write
Offset:
0x10
Reset value:
0x00000000
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• START: Receive Start Selection
31
30
29
28
27
26
25
24
PERIOD
23
22
21
20
19
18
17
16
STTDLY
15
14
13
12
11
10
9
8
–
–
–
STOP
START
7
6
5
4
3
2
1
0
CKG
CKI
CKO
CKS
START
Receive Start
0x0
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
0x1
Transmit start
0x2
Detection of a low level on RX_FRAME_SYNC signal
0x3
Detection of a high level on RX_FRAME_SYNC signal
0x4
Detection of a falling edge on RX_FRAME_SYNC signal
0x5
Detection of a rising edge on RX_FRAME_SYNC signal
0x6
Detection of any level change on RX_FRAME_SYNC signal
0x7
Detection of any edge on RX_FRAME_SYNC signal
0x8
Compare 0
0x9-0xF
Reserved
32058K AVR32-01/12