Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
282
AT32UC3A
25.9.5
Transmit Clock Mode Register
Name:
TCMR
Access Type:
Read/Write
Offset:
0x18
Reset value:
0x00000000
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission
of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit-
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit-
ted instead of the end of TAG.
• START: Transmit Start Selection
31
30
29
28
27
26
25
24
PERIOD
23
22
21
20
19
18
17
16
STTDLY
15
14
13
12
11
10
9
8
–
–
–
–
START
7
6
5
4
3
2
1
0
CKG
CKI
CKO
CKS
START
Transmit Start
0x0
Continuous, as soon as a word is written in the THR Register (if Transmit is enabled), and immediately
after the end of transfer of the previous data.
0x1
Receive start
0x2
Detection of a low level on TX_FRAME_SYNC signal
0x3
Detection of a high level on TX_FRAME_SYNC signal
0x4
Detection of a falling edge on TX_FRAME_SYNC signal
0x5
Detection of a rising edge on TX_FRAME_SYNC signal
0x6
Detection of any level change on TX_FRAME_SYNC signal
0x7
Detection of any edge on TX_FRAME_SYNC signal
0x8 - 0xF
Reserved
32058K AVR32-01/12