Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
417
AT32UC3A
28.7
Functional Description
28.7.1
SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. In both cases, the SDRAM control-
ler keeps track of the active row in each bank, thus maximizing performance. To initiate a burst
access, the SDRAM Controller uses the transfer type signal provided by the master requesting
the access. If the next access is a sequential write access, writing to the SDRAM device is car-
ried out. If the next access is a write-sequential access, but the current access is to a boundary
page, or if the next access is in another row, then the SDRAM Controller generates a precharge
command, activates the new row and initiates a write command. To comply with SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (t
RP
) commands and
active/write (t
RCD
) commands. For definition of these timing parameters, refer to the
. This is described in
below.
Figure 28-5.
Write Burst, 32-bit SDRAM Access
28.7.2
SDRAM Controller Read Cycle
The SDRAM Controller allows burst access, incremental burst of unspecified length or single
access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus
maximizing performance of the SDRAM. If row and bank addresses do not match the previous
row/bank address, then the SDRAM controller automatically generates a precharge command,
activates the new row and starts the read command. To comply with the SDRAM timing param-
eters, additional clock cycles on SDCK are inserted between precharge and active commands
(t
RP
) and between active and read command (t
RCD
). These two parameters are set in the config-
uration register of the SDRAM Controller. After a read command, additional wait states are
generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration
register).
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
t
RCD
= 3
Dna
SDWE
Dnb
Dnc
Dnd
Dne
Dnf
Dng
Dnh
Dni
Dnj
Dnk
Dnl
Row n
col a
col b
col c col d col e
col f
col g col h col i
col j
col k
col l
32058K
AVR32-01/12