Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
677
AT32UC3A
The clock generator is divided in three blocks:
– a modulo n counter which provides 11 clocks: F
MCK
, F
MCK
/2, F
MCK
/4, F
MCK
/8, F
MCK
/16,
F
MCK
/32, F
MCK
/64, F
MCK
/128, F
MCK
/256, F
MCK
/512, F
MCK
/1024
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Mode register (MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB)
field value in the PWM Mode register (MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register
are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Management
Controller.
32.6.2
PWM Channel
32.6.2.1
Block Diagram
Figure 32-3.
Functional View of the Channel Block Diagram
Each of the 7 channels is composed of three blocks:
• A clock selector which selects one of the clocks provided by the clock generator described in
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is
incremented or decremented according to the channel configuration and comparators events.
The size of the internal counter is 20 bits.
• A comparator used to generate events according to the internal counter value. It also computes
the PWMx output waveform according to the configuration.
32.6.2.2
Waveform Properties
The different properties of output waveforms are:
• the
• the
internal clock selection
. The internal channel counter is clocked by one of the clocks
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the CMRx register. This field is reset at 0.
• the
waveform period
. This channel parameter is defined in the CPRD field of the CPRDx
register.
Comparator
PWMx output waveform
Internal
Counter
Clock
Selector
inputs
from clock
generator
inputs from
Peripheral
Bus
Channel
32058K
AVR32-01/12