Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet

Product codes

ATEVK1105

734

AT32UC3A

35. On-Chip Debug

Rev: 1.3.0.0

35.1

Features

•

Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+

•

JTAG access to all on-chip debug functions

•

Advanced Program, Data, Ownership, and Watchpoint trace supported

•

NanoTrace JTAG-based trace access

•

Auxiliary port for high-speed trace information

•

Hardware support for 6 Program and 2 Data breakpoints

•

Unlimited number of software breakpoints supported

•

Automatic CRC check of memory regions

35.2

Overview

Debugging on the AT32UC3A is facilitated by a powerful On-Chip Debug (OCD) system. The

user accesses this through an external debug tool which connects to the JTAG port and the Aux-

iliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based

debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:

• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace

In addition to the mandatory Nexus debug features, the AT32UC3A implements several useful

OCD features, such as:

• Debug Communication Channel between CPU and JTAG
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support

The OCD features are controlled by OCD registers, which can be accessed by JTAG when the

NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly

using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based

on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical

Reference Manual.

32058K

AVR32-01/12