Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
583
42023E–SAM–07/2013
ATSAM4L8/L4/L2
24.6.3.2
Multidrop Mode
If MR.PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates
data and address characters. Data has the parity bit zero and addresses have a one. By writing
a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR
to be transmitted as an address. Receiving a character with a one as parity bit will report parity
error by setting CSR.PARE. An interrupt request is generated if the PARE bit in the Interrupt
Mask Register is set (IMR.PARE).
data and address characters. Data has the parity bit zero and addresses have a one. By writing
a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR
to be transmitted as an address. Receiving a character with a one as parity bit will report parity
error by setting CSR.PARE. An interrupt request is generated if the PARE bit in the Interrupt
Mask Register is set (IMR.PARE).
24.6.3.3
Transmitter Timeguard
The timeguard feature enables the USART to interface slow devices by inserting an idle state on
the TXD line in between two characters. This idle state corresponds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TTGR.TG bit periods, in addition to
the number of stop bits. As illustrated in
the TXD line in between two characters. This idle state corresponds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TTGR.TG bit periods, in addition to
the number of stop bits. As illustrated in
, the behavior of TXRDY and TXEMPTY is
modified when TG has a non-zero value. If a pending character has been written to THR, the
CSR.TXRDY bit will not be set until this characters start bit has been sent. CSR.TXEMPTY will
remain low until the timeguard transmission has completed.
CSR.TXRDY bit will not be set until this characters start bit has been sent. CSR.TXEMPTY will
remain low until the timeguard transmission has completed.
Figure 24-10. Timeguard Operation
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Start
Bit
TG = 4
Write
THR
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TXRDY
TXEMPTY
TG = 4
Table 24-5.
Maximum Baud Rate Dependent Timeguard Durations
Baud Rate (bit/sec)
Bit time (µs)
Timeguard (ms)
1 200
833
212.50
9 600
104
26.56
14400 69.4
17.71
19200
52.1
13.28
28800
34.7
8.85
33400
29.9
7.63
56000
17.9
4.55
57600
17.4
4.43
115200
8.7
2.21