Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
585
42023E–SAM–07/2013
ATSAM4L8/L4/L2
24.6.3.5
Framing Error
The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit
reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing
error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.
An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register
(IMR.FRAME) is set. CSR.FRAME is cleared by writing a one to CR.RSTSTA.
reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing
error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.
An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register
(IMR.FRAME) is set. CSR.FRAME is cleared by writing a one to CR.RSTSTA.
Figure 24-12. Framing Error Status
24.6.3.6
Transmit Break
When CSR.TXRDY is set, the user can request the transmitter to generate a break condition on
the TXD line by writing a one to the Start Break bit (CR.STTBRK). The break is treated as a nor-
mal 0x00 character transmission, clearing CSR.TXRDY and CSR.TXEMPTY, but with zeroes for
preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit (CR.STT-
BRK) will stop the generation of new break characters, and send ones for TG duration or at least
12 bit periods, ensuring that the receiver detects end of break, before resuming normal opera-
tion.
the TXD line by writing a one to the Start Break bit (CR.STTBRK). The break is treated as a nor-
mal 0x00 character transmission, clearing CSR.TXRDY and CSR.TXEMPTY, but with zeroes for
preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit (CR.STT-
BRK) will stop the generation of new break characters, and send ones for TG duration or at least
12 bit periods, ensuring that the receiver detects end of break, before resuming normal opera-
tion.
illustrates CR.STTBRK and CR.STPBRK effect on the TXD line.
Writing to CR.STTBRK and CR.STPBRK simultaneously can lead to unpredictable results.
Writes to THR before a pending break has started will be ignored.
Writes to THR before a pending break has started will be ignored.
Figure 24-13. Break Transmission
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
CR
FRAME
RXRDY
RSTSTA = 1
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission
End of Break