Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. 

This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud
rate of CLK_SPI divided by 255.

Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbid-
den. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. 

At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing
the first transfer.

The divisor can be defined independently for each chip select, as it has to be configured in the
CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced
peripheral without reprogramming. 

 shows a chip select transfer change and consecutive transfers on the

same chip select. Three delays can be configured to modify the transfer waveforms:

• The delay between chip selects, programmable only once for all the chip selects by writing to 

the Delay Between Chip Selects field in the MR register (MR.DLYBCS). Allows insertion of a 
delay between release of one chip select and before assertion of a new one.

• The delay before SPCK, independently programmable for each chip select by writing the 

Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to 
be delayed after the chip select has been asserted.

• The delay between consecutive transfers, independently programmable for each chip select 

by writing the Delay Between Consecutive Transfers field in the CSRn registers 
(CSRn.DLYBCT). Allows insertion of a delay between two transfers occurring on the same 
chip select

These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.

Figure 26-7. Programmable Delays

DLYBCS

DLYBS

DLYBCT

DLYBCT

Chip Select 1

Chip Select 2

SPCK