Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

CR

Write-only

0x00

0x00000000

The Control Register should only be written to enable the IISC after the chosen configuration has been written to the Mode
Register, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR
register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR.

Writing a zero to this bit has no effect.

Writing a one to this bit resets all the registers in the module. The module will be disabled after the reset.

This bit always reads as zero.

Writing a zero to this bit has no effect.

Writing a one to this bit disables the IISC Transmitter. SR.TXEN will be cleared when the Transmitter is effectively stopped.

Writing a zero to this bit has no effect.

Writing a one to this bit enables the IISC Transmitter, if TXDIS is not one. SR.TXEN will be set when the Transmitter is effectively 

started.

Writing a zero to this bit has no effect.

Writing a one to this bit disables the IISC clocks generation.

Writing a zero to this bit has no effect.

Writing a one to this bit enables the IISC clocks generation, if CKDIS is not one.

Writing a zero to this bit has no effect.

Writing a one to this bit disables the IISC Receiver. SR.TXEN will be cleared when the Transmitter is effectively stopped.

Writing a zero to this bit has no effect.

Writing a one to this bit enables the IISC Receiver, if RXDIS is not one. SR.RXEN will be set when the Receiver is effectively 

started.

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

-

-

-

-

-

-

-

-

15

14

13

12

11

10

9

8

-

-

-

-

-

-

-

-

7

6

5

4

3

2

1

0

SWRST

-

TXDIS

TXEN

CKDIS

CKEN

RXDIS

RXEN