Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023E–SAM–07/2013

MR

Read/Write

0x04

0x00000000

The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK,
and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to dis-
able the IISC before writing a new value into MR.

0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit.

1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit.

Refer to 

.

0: No Master Clock generated (generic clock is used as ISCK output).

1: Master Clock generated (generic clock is used as IMCK output).

Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to 

Master Clock frequency is 16*(IMCKFS+1) times the sample rate, i.e. IWS frequency:

31

30

29

28

27

26

25

24

IWS24

IMCKMODE

IMCKFS

23

22

21

20

19

18

17

16

-

-

-

-

-

-

-

-

15

14

13

12

11

10

9

8

-

TXSAME

TXDMA

TXMONO

RXLOOP

RXDMA

RXMONO

7

6

5

4

3

2

1

0

-

-

-

DATALENGTH

-

MODE

Master Clock to Sample Frequency (fs) Ratio

16 fs

0

32 fs

1

48fs

2

64 fs

3

96fs

5

128 fs

7

192fs

11

256 fs

15