Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

from the Timer Busy field of the SR register (SR.TBUSY): 0 means stopped, 1 means running. In
addition when the internal timer is running, if ITIMER.ITMC is written to change the internal timer
timeout frequency, the internal counter is cleared to avoid rollover phenomena.

Note: It is possible to generate an internal timer event each GCLK period by writing 0 in
ITIMER.ITMC and by selecting the internal timer as a STRIG source

There are two PDCA channels. One Rx for transferring data result to memory, and one Tx for
storing the updated configuration of the next conversion from memory.

The LCV register contains the last converted value of the sequencer according to the conversion
result format. The LCV register is updated each time the sequencer ends a conversion. If the
last converted value has not been read, there’s an overrun, the LOVR bit in the SR register indi-
cates that at least one overrun error occurred. The LOVR bit of the SR register is cleared by
writing a ‘1’ in the LOVR field of the SCR register.

Tx transfer: If the configuration is performed by the PDCA, so the CDMA register contains con-
figuration for the next conversion. If Window Mode is not used, only one word is usefull with the
MSB bit to zero. If Window Mode is used, the first word has the MSB bit to one and the second
word is dedicated for Window Mode with MSB bit set to zero.

Note: Rx PDCA transfers are 16 bits wide.

Note: In Tx, the first word received has always the same structure. The second word, if neces-
sary, has always the same structure too.

Figure 38-2. One DMA Tx transfer: No Window Mode Configuration

MSB : 0

DMA Tx Ready

APB Data Bus

DMA Word Data

Start Of Conversion

31

30

29

28

27

26

25

24

0

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

TSS

RES

ENSTUP

7

6

5

4

3

2

1

0

GCOMP

STRIG

BIPOLAR

HWLA

GAIN

ZOOMRANGE

MUXNEG

INTERNAL

MUXPOS

DMA Word Data with MSB to "0"

CDMA Register