Data Sheet (ATSAM4L-EK)Table of ContentsSummary1Features11. Description32. Overview52.1 Block Diagram52.2 Configuration Summary63. Package and Pinout83.1 Package83.1.1 ATSAM4LCx Pinout83.1.2 ATSAM4LSx Pinout133.2 Peripheral Multiplexing on I/O lines183.2.1 Multiplexed Signals183.2.2 Peripheral Functions283.2.3 JTAG Port Connections283.2.4 ITM Trace Connections293.2.5 Oscillator Pinout293.3 Signals Description303.4 I/O Line Considerations333.4.1 SW/JTAG Pins333.4.2 RESET_N Pin333.4.3 TWI Pins333.4.4 GPIO Pins333.4.5 High-drive Pins333.4.6 USB Pins333.4.7 ADC Input Pins344. Cortex-M4 processor and core peripherals354.1 Cortex-M4354.2 System level interface364.3 Integrated configurable debug364.4 Cortex-M4 processor features and benefits summary374.5 Cortex-M4 core peripherals374.6 Cortex-M4 implementations options384.7 Cortex-M4 Interrupts map384.8 Peripheral Debug414.8.1 Peripheral Debug415. Memories425.1 Product Mapping425.2 Embedded Memories435.3 Physical Memory Map436. Power and Startup Considerations456.1 Power Domain Overview456.2 Power Supplies476.2.1 Voltage Regulator476.2.2 Typical Powering Schematics486.2.3 LCD Power Modes496.2.3.1 Principle496.2.3.2 Internal LCD Voltage506.2.4 Power-up Sequence526.2.4.1 Maximum Rise Rate526.2.4.2 Minimum Rise Rate526.3 Startup Considerations526.3.1 Starting of Clocks526.3.2 Fetching of Initial Instructions526.4 Power-on-Reset, Brownout and Supply Monitor526.4.1 Power-on-Reset on VDDANA536.4.2 Brownout Detector on VDDANA536.4.3 Power-on-Reset on VDDCORE536.4.4 Brownout Detector on VDDCORE537. Low Power Techniques547.1 Power Save Modes547.1.1 SLEEP mode557.1.1.1 Entering SLEEP mode557.1.1.2 Exiting SLEEP mode567.1.2 WAIT Mode and RETENTION Mode567.1.2.1 Entering WAIT or RETENTION Mode567.1.2.2 Exiting WAIT or RETENTION Mode567.1.3 BACKUP Mode577.1.3.1 Entering BACKUP Mode577.1.3.2 Exiting BACKUP Mode577.1.4 Wakeup Time587.1.4.1 Wakeup Time From SLEEP Mode587.1.4.2 Wakeup Time From WAIT or RETENTION Mode587.1.4.3 Wake time from BACKUP mode587.1.5 Power Save Mode Summary Table597.2 Power Scaling598. Debug and Test618.1 Features618.2 Overview618.3 Block diagram628.4 I/O Lines Description628.5 Product dependencies638.5.1 I/O Lines638.5.2 Power management638.5.3 Clocks638.6 Core debug638.6.1 FPB (Flash Patch Breakpoint)638.6.2 DWT (Data Watchpoint and Trace)648.6.3 ITM (Instrumentation Trace Macrocell)648.7 Enhanced Debug Port (EDP)668.7.1 Features668.7.2 Overview668.7.3 Block Diagram678.7.4 I/O Lines Description678.7.5 Product Dependencies688.7.5.1 I/O Lines688.7.5.2 Power Management688.7.5.3 Clocks688.7.6 Module Initialization688.7.7 Debugger Hot Plugging688.7.8 SMAP Core Reset Request Source698.7.9 SWJ-DP698.7.10 SW-DP and JTAG-DP Selection Mechanism708.7.11 JTAG-DP and BSCAN-TAP Selection Mechanism708.7.12 JTAG Instructions Summary718.7.13 Security Restrictions728.7.13.1 Notation728.7.14 JTAG Instructions738.7.14.1 EXTEST738.7.14.2 SAMPLE_PRELOAD738.7.14.3 INTEST748.7.14.4 CLAMP758.8 AHB-AP Access Port768.9 System Manager Access Port (SMAP)778.9.1 Features778.9.2 Overview778.9.3 Block Diagram778.9.4 Initializing the Module778.9.5 Stopping the Module778.9.6 Security Considerations788.9.7 Chip Erase788.9.8 Cortex-M4 Core Reset Source788.9.9 Unlimited Flash User Page Read Access798.9.10 32-bit Cyclic Redundancy Check (CRC)798.9.10.1 Starting CRC Calculation798.9.10.2 Interpreting the Results798.9.11 SMAP User Interface808.9.11.1 Control Register818.9.11.2 Status Register828.9.11.3 Status Clear Register848.9.11.4 Address Register858.9.11.5 Length Register868.9.11.6 Data Register878.9.11.7 Module Version888.9.11.8 Chip Identification Register898.9.11.9 Chip Identification Extension Register908.9.11.10 Identification Register918.10 Available Features in Protected State928.11 Functional Description938.11.1 Debug Environment938.11.2 Test Environment938.11.3 How to initialize test and debug features948.11.4 How to disable test and debug features948.11.5 Typical JTAG sequence948.11.5.1 Scanning in JTAG instruction948.11.5.2 Scanning in/out data958.11.6 Boundary-Scan958.11.7 Flash Programming typical procedure968.11.8 Chip erase typical procedure978.11.9 Setting the protected state979. Electrical Characteristics989.1 Absolute Maximum Ratings*989.2 Operating Conditions989.3 Supply Characteristics989.4 Maximum Clock Frequencies1009.5 Power Consumption1029.5.1 Power Scaling 0 and 21029.5.2 Power Scaling 11049.5.3 Peripheral Power Consumption in Power Scaling mode 0 and 21099.5.4 .Peripheral Power Consumption in Power Scaling mode 11109.6 I/O Pin Characteristics1139.6.1 Normal I/O Pin1139.6.2 High-drive I/O Pin : PA02, PC04, PC05, PC061149.6.3 USB I/O Pin : PA25, PA261159.6.4 TWI Pin : PA21, PA22, PA23, PA24, PB14, PB151159.6.5 High Drive TWI Pin : PB00, PB011189.7 Oscillator Characteristics1209.7.1 Oscillator 0 (OSC0) Characteristics1209.7.1.1 Digital Clock Characteristics1209.7.1.2 Crystal Oscillator Characteristics1209.7.2 32 kHz Crystal Oscillator (OSC32K) Characteristics1229.7.3 Phase Locked Loop (PLL) Characteristics1239.7.4 Digital Frequency Locked Loop (DFLL) Characteristics1239.7.5 32 kHz RC Oscillator (RC32K) Characteristics1249.7.6 System RC Oscillator (RCSYS) Characteristics1249.7.7 1MHz RC Oscillator (RC1M) Characteristics1259.7.8 4/8/12MHz RC Oscillator (RCFAST) Characteristics1259.7.9 80MHz RC Oscillator (RC80M) Characteristics1269.8 Flash Characteristics1269.9 Analog Characteristics1289.9.1 Voltage Regulator Characteristics1289.9.2 Power-on Reset 33 Characteristics1309.9.3 Brown Out Detectors Characteristics1309.9.4 Analog- to Digital Converter Characteristics1329.9.4.1 Inputs and Sample and Hold Acquisition Times1359.9.5 Digital to Analog Converter Characteristics1369.9.6 Analog Comparator Characteristics1369.9.7 Liquid Crystal Display Controler characteristics1389.9.7.1 Liquid Crystal Controler supply current1389.10 Timing Characteristics1399.10.1 RESET_N Timing1399.10.2 USART in SPI Mode Timing1399.10.2.1 Master mode1399.10.2.2 Slave mode1419.10.3 SPI Timing1459.10.3.1 Master mode1459.10.3.2 Slave mode1469.10.4 TWIM/TWIS Timing1489.10.5 JTAG Timing1499.10.6 SWD Timing15010. Mechanical Characteristics15210.1 Thermal Considerations15210.1.1 Thermal Data15210.1.2 Junction Temperature15210.2 Package Drawings15310.3 Soldering Profile16211. Ordering Information16312. Errata16612.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A16612.1.1 General16612.1.2 SCIF16612.1.3 WDT16612.1.4 SPI16612.1.5 TC16712.1.6 USBC16712.1.7 FLASHCALW16813. Datasheet Revision History16913.1 Rev. A – 09/1216913.2 Rev. B – 10/1216913.3 Rev. C – 02/1316913.4 Rev. D – 03/1316913.5 Rev. E – 07/13170Table of Contents171Size: 2.72 MBPages: 173Language: EnglishOpen manual
Data Sheet (ATSAM4L-EK)Table of ContentsSummary1Features11. Description32. Overview52.1 Block Diagram52.2 Configuration Summary63. Package and Pinout83.1 Package83.1.1 ATSAM4LCx Pinout83.1.2 ATSAM4LSx Pinout133.2 Peripheral Multiplexing on I/O lines183.2.1 Multiplexed Signals183.2.2 Peripheral Functions283.2.3 JTAG Port Connections283.2.4 ITM Trace Connections293.2.5 Oscillator Pinout293.3 Signals Description303.4 I/O Line Considerations333.4.1 SW/JTAG Pins333.4.2 RESET_N Pin333.4.3 TWI Pins333.4.4 GPIO Pins333.4.5 High-drive Pins333.4.6 USB Pins333.4.7 ADC Input Pins344. Cortex-M4 processor and core peripherals354.1 Cortex-M4354.2 System level interface364.3 Integrated configurable debug364.4 Cortex-M4 processor features and benefits summary374.5 Cortex-M4 core peripherals374.6 Cortex-M4 implementations options384.7 Cortex-M4 Interrupts map384.8 Peripheral Debug414.8.1 Peripheral Debug415. Power and Startup Considerations425.1 Power Domain Overview425.2 Power Supplies445.2.1 Voltage Regulator445.2.2 Typical Powering Schematics455.2.3 LCD Power Modes465.2.3.1 Principle465.2.3.2 Internal LCD Voltage475.2.4 Power-up Sequence495.2.4.1 Maximum Rise Rate495.2.4.2 Minimum Rise Rate495.3 Startup Considerations495.3.1 Starting of Clocks495.3.2 Fetching of Initial Instructions495.4 Power-on-Reset, Brownout and Supply Monitor495.4.1 Power-on-Reset on VDDANA505.4.2 Brownout Detector on VDDANA505.4.3 Power-on-Reset on VDDCORE505.4.4 Brownout Detector on VDDCORE506. Low Power Techniques516.1 Power Save Modes516.1.1 SLEEP mode526.1.1.1 Entering SLEEP mode526.1.1.2 Exiting SLEEP mode536.1.2 WAIT Mode and RETENTION Mode536.1.2.1 Entering WAIT or RETENTION Mode536.1.2.2 Exiting WAIT or RETENTION Mode536.1.3 BACKUP Mode546.1.3.1 Entering BACKUP Mode546.1.3.2 Exiting BACKUP Mode546.1.4 Wakeup Time556.1.4.1 Wakeup Time From SLEEP Mode556.1.4.2 Wakeup Time From WAIT or RETENTION Mode556.1.4.3 Wake time from BACKUP mode556.1.5 Power Save Mode Summary Table566.2 Power Scaling567. Memories587.1 Product Mapping587.2 Embedded Memories597.3 Physical Memory Map598. Debug and Test618.1 Features618.2 Overview618.3 Block Diagram628.4 I/O Lines Description628.5 Product Dependencies638.5.1 I/O Lines638.5.2 Power Management638.5.3 Clocks638.6 Core Debug638.6.1 FPB (Flash Patch Breakpoint)638.6.2 DWT (Data Watchpoint and Trace)648.6.3 ITM (Instrumentation Trace Macrocell)648.7 Enhanced Debug Port (EDP)668.7.1 Features668.7.2 Overview668.7.3 Block Diagram678.7.4 I/O Lines Description678.7.5 Product Dependencies688.7.5.1 I/O Lines688.7.5.2 Power Management688.7.5.3 Clocks688.7.6 Module Initialization688.7.7 Debugger Hot Plugging688.7.8 SMAP Core Reset Request Source698.7.9 SWJ-DP698.7.10 SW-DP and JTAG-DP Selection Mechanism708.7.11 JTAG-DP and BSCAN-TAP Selection Mechanism708.7.12 JTAG Instructions Summary718.7.13 Security Restrictions728.7.13.1 Notation728.7.14 JTAG Instructions738.7.14.1 EXTEST738.7.14.2 SAMPLE_PRELOAD738.7.14.3 INTEST748.7.14.4 CLAMP758.8 System Manager Access Port (SMAP)768.8.1 Features768.8.2 Overview768.8.3 Block Diagram768.8.4 Initializing the Module768.8.5 Stopping the Module768.8.6 Security Considerations778.8.7 Chip Erase778.8.8 Cortex-M4 Core Reset Source778.8.9 Unlimited Flash User Page Read Access788.8.10 32-bit Cyclic Redundancy Check (CRC)788.8.10.1 Starting CRC Calculation788.8.10.2 Interpreting the Results788.8.11 SMAP User Interface798.8.11.1 Control Register808.8.11.2 Status Register818.8.11.3 Status Clear Register838.8.11.4 Address Register848.8.11.5 Length Register858.8.11.6 Data Register868.8.11.7 Module Version878.8.11.8 Chip Identification Register888.8.11.9 Chip Identification Extension Register898.8.11.10 Identification Register908.9 AHB-AP Access Port918.10 Available Features in Protected State928.11 Functional Description938.11.1 Debug Environment938.11.2 Test Environment938.11.3 How to Initialize Test and Debug Features948.11.4 How to Disable Test and Debug Features948.11.5 Typical JTAG Sequence948.11.5.1 Scanning in JTAG Instruction948.11.5.2 Scanning In/Out Data958.11.6 Boundary-Scan958.11.7 Flash Programming Typical Procedure968.11.8 Chip Erase Typical Procedure978.11.9 Setting the Protected State979. Chip Identifier (CHIPID)989.1 Description989.2 Embedded Characteristics989.3 User Interface1009.3.1 Chip ID Register1019.3.2 Extension Register10610. Power Manager (PM)10810.1 Features10810.2 Overview10810.3 Block Diagram10810.4 I/O Lines Description10910.5 Product Dependencies10910.5.1 Interrupt10910.5.2 Clock Implementation10910.6 Functional Description10910.6.1 Synchronous Clocks10910.6.1.1 Selecting the Main Clock Source11010.6.1.2 Selecting Synchronous Clock Division Ratio11010.6.1.3 Clock Ready Flag11110.6.2 Peripheral Clock Masking11110.6.2.1 Cautionary Note11110.6.2.2 SleepWalking™11110.6.3 Speeding-up Sleep Modes Wake Up Times11210.6.4 Divided APB Clocks11210.6.5 Reset Controller11210.6.6 Clock Failure Detector11310.6.7 Interrupts11310.7 User Interface11510.7.1 Main Clock Control11610.7.2 CPU Clock Select11710.7.3 PBx Clock Select11810.7.4 Clock Mask11910.7.5 Divided Clock Mask12110.7.6 Clock Failure Detector Control Register12210.7.7 PM Unlock Register12310.7.8 Interrupt Enable Register12410.7.9 Interrupt Disable Register12510.7.10 Interrupt Mask Register12610.7.11 Interrupt Status Register12710.7.12 Interrupt Clear Register12810.7.13 Status Register12910.7.14 Peripheral Power Control Register13010.7.15 Reset Cause13210.7.16 Wake Cause Register13310.7.17 Asynchronous Wake Up Enable Register13410.7.18 Fast Sleep Register13510.7.19 Configuration Register13610.7.20 Version Register13710.8 Module Configuration13811. Backup Power Manager (BPM)13911.1 Features13911.2 Overview13911.3 Block Diagram14011.4 Product Dependencies14011.4.1 Clocks14011.4.2 Interrupts14111.4.3 Debug Operation14111.5 Functional Description14111.5.1 Power Scaling14111.5.2 Power Save Modes14111.5.3 I/O Lines Pin Muxing in Backup Mode14111.5.4 I/O Lines Retention in Backup Mode14211.5.5 Wakeup From BACKUP Mode14211.5.6 Precautions When Entering Power Save Mode.14311.5.7 Interrupts14311.6 User Interface14411.6.1 Interrupt Enable Register14511.6.2 Interrupt Disable Register14611.6.3 Interrupt Mask Register14711.6.4 Interrupt Status Register14811.6.5 Interrupt Clear Register14911.6.6 Status Register15011.6.7 Unlock Register15111.6.8 Power Mode Control Register15211.6.9 Backup Wake up Cause Register15411.6.10 Backup Wake up Enable Register15511.6.11 Backup Pin Muxing Register15611.6.12 Input Output Retention Register15711.6.13 Version Register15811.7 Module Configuration15912. Backup System Control Interface (BSCIF)16012.1 Features16012.2 Overview16012.3 Block Diagram16112.4 I/O Lines Description16112.5 Product Dependencies16212.5.1 Power Management16212.5.2 Clocks16212.5.3 Interrupts16212.5.4 Debug Operation16212.6 Functional Description16212.6.1 32 KHz Oscillator (OSC32K) Operation16212.6.2 32 KHz RC Oscillator (RC32K)16312.6.3 Brow-Out Detector (BOD) Operation16412.6.3.1 Monitored Voltages16512.6.3.2 Supported Modes16512.6.3.3 Continuous Mode16612.6.3.4 Sampling Mode16612.6.3.5 Clock Sources16612.6.3.6 Changing Clock Source16712.6.3.7 Changing the Prescaler16712.6.3.8 BOD18/33 Interrupts/Reset16712.6.3.9 Hysteresis16712.6.3.10 BOD18 Threshold Ranges16712.6.3.11 Power Save Modes16812.6.3.12 Flash Fuses16812.6.4 Voltage Regulator (VREG)16812.6.4.1 Register Protection16812.6.4.2 1MHz RC Oscillator16912.6.5 Bandgap16912.6.6 Backup Registers (BR)16912.6.7 Interrupts16912.7 User Interface17112.7.1 Interrupt Enable Register17212.7.2 Interrupt Disable Register17312.7.3 Interrupt Mask Register17412.7.4 Interrupt Status Register17512.7.5 Interrupt Clear Register17612.7.6 Power and Clocks Status Register17712.7.7 Unlock Register17912.7.8 32 KHz Oscillator Control Register18012.7.9 32 KHz RC Oscillator Control Register18312.7.10 RC32K Tuning Register18412.7.11 BOD Control Register18512.7.12 BOD Sampling Control Register18712.7.13 BOD Level Register18812.7.14 Voltage Regulator Configuration Register18912.7.15 1MHz RC Clock Configuration Register19012.7.16 Bandgap Control Register19112.7.17 Bandgap Status Register19212.7.18 Backup Register n19312.7.19 Backup Register Interface Version Register19412.7.20 Bandgap Reference Interface Version Register19512.7.21 Voltage Regulator Version Register19612.7.22 Brown-Out Detector Version Register19712.7.23 32kHz RC Oscillator Version Register19812.7.24 32kHz Oscillator Version Register19912.7.25 BSCIF Version Register20012.8 Module Configuration20113. System Control Interface (SCIF)20213.1 Features20213.2 Overview20213.3 Block Diagram20213.4 I/O Lines Description20313.5 Product Dependencies20313.5.1 I/O Lines20313.5.2 Power Management20313.5.3 Clocks20313.5.4 Interrupts20313.5.5 Debug Operation20313.6 Functional Description20313.6.1 Oscillator (OSC) Operation20313.6.2 PLL Operation20413.6.2.1 Enabling the PLL20513.6.2.2 Disabling the PLL20513.6.2.3 PLL Lock20513.6.3 Digital Frequency Locked Loop (DFLL) Operation20613.6.3.1 Enabling the DFLL20713.6.3.2 Internal Synchronization20713.6.3.3 Disabling the DFLL20713.6.3.4 Open Loop Operation20713.6.3.5 Closed Loop Operation20813.6.3.6 Dealing With Delay in the DFLL21013.6.3.7 Spread Spectrum Generator (SSG)21013.6.3.8 Wake From Power Save Modes21113.6.3.9 Accuracy21213.6.4 System RC Oscillator (RCSYS)21213.6.5 4/8/12MHz RC Oscillator (RCFAST) Operation21213.6.5.1 Product Dependencies21313.6.5.2 General Use21313.6.5.3 Open Loop Mode21313.6.5.4 Closed Loop Mode21413.6.5.5 Factory Calibration21413.6.5.6 Register Protection21413.6.6 80MHz RC Oscillator (RC80M) Operation21413.6.7 Generic Clock Prescalers21513.6.7.1 High Resolution Prescaler21513.6.7.2 Fractional Prescaler21513.6.8 Generic Clocks21613.6.8.1 Enabling a Generic Clock21713.6.8.2 Disabling a Generic Clock21713.6.8.3 Changing Clock Frequency21713.6.8.4 Generic Clock Allocation21813.6.9 Interrupts21813.7 User Interface21913.7.1 Interrupt Enable Register22113.7.2 Interrupt Disable Register22213.7.3 Interrupt Mask Register22313.7.4 Interrupt Status Register22413.7.5 Interrupt Clear Register22513.7.6 Power and Clocks Status Register22613.7.7 Unlock Register22813.7.8 Oscillator Control Register22913.7.9 PLL Control Register23013.7.10 DFLLx Configuration Register23213.7.11 DFLLx Value Register23313.7.12 DFLLx Multiplier Register23413.7.13 DFLLx Maximum Step Register23513.7.14 DFLLx Spread Spectrum Generator Control Register23613.7.15 DFLLx Ratio Register23713.7.16 DFLLx Synchronization Register23813.7.17 System RC Oscillator Calibration Register23913.7.18 4/8/12MHz RC Oscillator Configuration Register24013.7.19 4/8/12MHz RC Oscillator Status Register24213.7.20 80MHz RC Oscillator Control Register24313.7.21 High Resolution Prescaler Control Register24413.7.22 Fractional Prescaler Control Register24513.7.23 Fractional Prescaler Mul Register24613.7.24 Fractional Prescaler Div Register24713.7.25 Generic Clock Control24813.7.26 4/8/12MHz RC Oscillator Version Register24913.7.27 Generic Clock Prescalers Version Register25013.7.28 PLL Version Register25113.7.29 Oscillator 0 Version Register25213.7.30 Digital Frequency Locked Loop Version Register25313.7.31 RC Oscillator Version Register25413.7.32 80MHz RC Oscillator Version Register25513.7.33 Generic Clock Version Register25613.7.34 SCIF Version Register25713.8 Module Configuration25814. Flash Controller (FLASHCALW)26214.1 Features26214.2 Overview26214.3 Block Diagram26314.4 Product Dependencies26314.4.1 Power Management26314.4.2 Clocks26314.4.3 Interrupts26414.4.4 Debug Operation26414.5 Functional Description26514.5.1 Bus Interfaces26514.5.2 Flash Memory Organization26614.5.3 User Page26614.5.4 Read Operations26614.5.5 High Speed Read Mode26814.5.6 Quick Page Read26914.5.7 Quick User Page Read26914.5.8 Page Buffer Operations27014.5.9 PicoCache Description27214.5.9.1 Overview27214.5.9.2 Cache Operation27214.5.9.3 Cache Invalidate By Line Operation27214.5.9.4 Cache Invalidate All Operation27214.5.9.5 Cache Performance Monitoring27214.5.10 Accessing the PicoCache Memory Block As a Regular Memory On the System Bus27214.6 Flash Commands27414.6.1 Write/Erase Page Operation27514.6.2 Erase All Operation27514.6.3 Region Lock Bits27614.7 General-purpose Fuse Bits27614.8 Security Fuses27714.9 Error Correcting Code27714.10 User Interface27914.10.1 Flash Control Register28014.10.2 Flash Command Register28114.10.3 Flash Status Register28314.10.4 Flash Parameter Register28414.10.5 Flash Version Register28614.10.6 Flash General Purpose Fuse Register High28714.10.7 Flash General Purpose Fuse Register Low28814.10.8 PicoCache Control Register28914.10.9 PicoCache Status Register29014.10.10 PicoCache Maintenance Register 029114.10.11 PicoCache Maintenance Register 129214.10.12 PicoCache Monitor Configuration Register29314.10.13 PicoCache Monitor Enable Register29414.10.14 PicoCache Monitor Control Register29514.10.15 PicoCache Monitor Status Register29614.10.16 PicoCache Version Register29714.11 Fuse Settings29814.11.1 Flash General Purpose Fuse Register Low (FGPFRLO)29914.11.2 First Word of the User Page (Address 0x808000004)30014.11.3 Second Word of the User Page (Address 0x80800000)30214.12 Serial Number30214.13 Module Configuration30215. HSB Bus Matrix (HMATRIXB)30415.1 Features30415.2 Overview30415.3 Product Dependencies30415.3.1 Clocks30415.4 Functional Description30415.4.1 Special Bus Granting Mechanism30415.4.1.1 No Default Master30515.4.1.2 Last Access Master30515.4.1.3 Fixed Default Master30515.4.2 Arbitration30515.4.2.1 Arbitration Rules30515.4.2.2 Round-Robin Arbitration30615.4.2.3 Fixed Priority Arbitration30715.4.3 Slave and Master Assignation30715.5 User Interface30815.5.1 Master Configuration Registers31115.5.2 Slave Configuration Registers31215.5.3 Bus Matrix Priority Registers A For Slaves31315.5.4 Priority Registers B For Slaves31415.5.5 Special Function Registers31515.6 Module Configuration31615.6.1 Bus Matrix Connections31616. Peripheral DMA Controller (PDCA)31816.1 Features31816.2 Overview31816.3 Block Diagram31916.4 Product Dependencies31916.4.1 Power Management31916.4.2 Clocks31916.4.3 Interrupts31916.4.4 Peripheral Events32016.5 Functional Description32016.5.1 Basic Operation32016.5.2 Memory Pointer32016.5.3 Transfer Counter32016.5.4 Reload Registers32016.5.5 Ring Buffer32116.5.6 Peripheral Selection32116.5.7 Transfer Size32116.5.8 Enabling and Disabling32116.5.9 Interrupts32116.5.10 Priority32216.5.11 Error Handling32216.5.12 Peripheral Event Trigger32216.6 User Interface32316.6.1 Memory Map Overview32316.6.2 Channel Memory Map32316.6.3 Version Register Memory Map32316.6.4 Memory Address Register32416.6.5 Peripheral Select Register32516.6.6 Transfer Counter Register32616.6.7 Memory Address Reload Register32716.6.8 Transfer Counter Reload Register32816.6.9 Control Register32916.6.10 Mode Register33016.6.11 Status Register33116.6.12 Interrupt Enable Register33216.6.13 Interrupt Disable Register33316.6.14 Interrupt Mask Register33416.6.15 Interrupt Status Register33516.6.16 PDCA Version Register33616.7 Module Configuration33717. USB Device and Embedded Host Interface (USBC)34017.1 Features34017.2 Overview34017.3 Block Diagram34017.4 I/O Lines Description34217.5 Product Dependencies34317.5.1 I/O Lines34317.5.2 Power Management34317.5.3 Clocks34317.5.4 Interrupts34317.6 Functional Description34417.6.1 USB General Operation34417.6.1.1 Initialization34417.6.1.2 Interrupts34517.6.1.3 Frozen clock34517.6.1.4 Speed control345• Device mode345• Host mode34517.6.1.5 Data management34517.6.1.6 Pad Suspend34617.6.2 USBC Device Mode Operation34717.6.2.1 Device Enabling34717.6.2.2 USB reset34717.6.2.3 Endpoint activation34717.6.2.4 Endpoint redirection34717.6.2.5 Data toggle sequence34717.6.2.6 Busy bank enable34817.6.2.7 Address setup34817.6.2.8 Suspend and Wakeup34817.6.2.9 Detach34817.6.2.10 Remote wakeup34917.6.2.11 RAM management34917.6.2.12 STALL request351• Special considerations for control endpoints351• STALL handshake and retry mechanism35117.6.2.13 Multi packet mode and single packet mode.35217.6.2.14 Management of control endpoints352• Overview352• Control write352• Control read35317.6.2.15 Management of IN endpoints354• Overview354• Detailed description355• Multi packet mode for IN endpoints35517.6.2.16 Management of OUT endpoints356• Overview356• Detailed description357• Multi packet mode for OUT endpoints35717.6.2.17 Data flow error35817.6.2.18 CRC error35817.6.2.19 Interrupts358• Global interrupts358• Endpoint interrupts35917.6.3 USB Host Operation36017.6.3.1 Host Enabling36017.6.3.2 Device detection36017.6.3.3 Description of pipes36017.6.3.4 USB reset36117.6.3.5 Pipe activation36117.6.3.6 Address setup36117.6.3.7 Remote wakeup36217.6.3.8 RAM management36217.6.3.9 Multi packet mode and single packet mode.36517.6.3.10 Management of control pipes36517.6.3.11 Management of IN pipes365• Overview365• Detailed description365• Multi packet mode for IN pipes36617.6.3.12 Management of OUT pipes366• Overview366• Detailed description366• Multi packet mode for OUT pipes36817.6.3.13 Alternate pipe36817.6.3.14 Data flow error36817.6.3.15 CRC error36817.6.3.16 Interrupts369• Global interrupts369• Pipe interrupts36917.7 User Interface37017.7.1 USB General Registers37217.7.1.1 General Control Register37217.7.1.2 General Status Register37317.7.1.3 General Status Clear Register37417.7.1.4 General Status Set Register37517.7.1.5 Version Register37617.7.1.6 Features Register37717.7.1.7 Address Size Register37817.7.1.8 IP Name Register 137917.7.1.9 IP Name Register 238017.7.1.10 Finite State Machine Status Register38117.7.1.11 USB Descriptor Address38317.7.2 USB Device Registers38417.7.2.1 Device General Control Register38417.7.2.2 Device Global Interrupt Register38517.7.2.3 Device Global Interrupt Clear Register38717.7.2.4 Device Global Interrupt Set Register38817.7.2.5 Device Global Interrupt Enable Register38917.7.2.6 Device Global Interrupt Enable Clear Register39017.7.2.7 Device Global Interrupt Enable Set Register39117.7.2.8 Endpoint Enable/Reset Register39217.7.2.9 Device Frame Number Register39317.7.2.10 Endpoint n Configuration Register39417.7.2.11 Endpoint n Status Register39617.7.2.12 Endpoint n Status Clear Register39917.7.2.13 Endpoint n Status Set Register40017.7.2.14 Endpoint n Control Register40117.7.2.15 Endpoint n Control Clear Register40317.7.2.16 Endpoint n Control Set Register40417.7.3 USB Host Registers40517.7.3.1 Host General Control Register40517.7.3.2 Host Global Interrupt Register40617.7.3.3 Host Global Interrupt Clear Register40817.7.3.4 Host Global Interrupt Set Register40917.7.3.5 Host Global Interrupt Enable Register41017.7.3.6 Host Global Interrupt Enable Clear Register41117.7.3.7 Host Global Interrupt Enable Set Register41217.7.3.8 Pipe Enable/Reset Register41317.7.3.9 Host Frame Number Register41417.7.3.10 Host Start Of Frame Control Register41517.7.3.11 Pipe n Configuration Register41617.7.3.12 Pipe n Status Register41817.7.3.13 Pipe n Status Clear Register42017.7.3.14 Pipe n Status Set Register42117.7.3.15 Pipe n Control Register42217.7.3.16 Pipe n Control Set Register42417.7.3.17 Pipe n Control Clear Register42517.7.3.18 Pipe n IN Request Register42617.8 Module Configuration42718. Advanced Encryption Standard (AESA)42818.1 Features42818.2 Overview42818.3 Product Dependencies42918.3.1 Power Management42918.3.2 Clocks42918.3.3 Interrupts42918.4 Functional Description42918.4.1 Basic Programming and Operation42918.4.2 Confidentiality Modes of Operation43118.4.3 DMA Interface43218.4.4 Computation of Last Nk Words of Expanded Key43218.4.5 Security Features43318.4.5.1 Hardware Countermeasures Against Differential Power Analysis Attacks43318.5 User Interface43418.5.1 Control Register43518.5.2 Mode Register43618.5.3 Data Buffer Pointer Register43818.5.4 Status Register43918.5.5 Interrupt Enable Register44018.5.6 Interrupt Disable Register44118.5.7 Interrupt Mask Register44218.5.8 Key Registers44318.5.9 Initialization Vector Registers44418.5.10 Input Data Register44518.5.11 Output Data Register44618.5.12 DRNG Seed Register44718.5.13 Parameter Register44818.5.14 Version Register44918.6 Module Configuration45019. Asynchronous Timer (AST)45119.1 Features45119.2 Overview45119.3 Block Diagram45219.4 Product Dependencies45219.4.1 Power Management45219.4.2 Clocks45219.4.3 Interrupts45319.4.4 Peripheral Events45319.4.5 Debug Operation45319.5 Functional Description45319.5.1 Initialization45319.5.1.1 Enabling and Disabling the AST Clock45319.5.1.2 Changing the Source Clock45419.5.2 Basic Operation45419.5.2.1 Prescaler45419.5.2.2 Counter Operation45419.5.2.3 Calendar Operation45519.5.3 Interrupts45519.5.3.1 Periodic Interrupt45519.5.3.2 Alarm Interrupt45619.5.4 Peripheral Events45619.5.5 AST wakeup45719.5.6 Backup Mode45719.5.7 Digital Tuner45719.5.8 Synchronization45819.6 User Interface45919.6.1 Control Register46019.6.2 Counter Value46119.6.3 Status Register46219.6.4 Status Clear Register46319.6.5 Interrupt Enable Register46419.6.6 Interrupt Disable Register46519.6.7 Interrupt Mask Register46619.6.8 Wake Enable Register46719.6.9 Alarm Register 046819.6.10 Alarm Register 146919.6.11 Periodic Interval Register 047019.6.12 Periodic Interval Register 147119.6.13 Clock Control Register47219.6.14 Digital Tuner Register47319.6.15 Event Enable Register47419.6.16 Event Disable Register47519.6.17 Event Mask Register47619.6.18 Calendar Value47719.6.19 Parameter Register47819.6.20 Version Register47919.7 Module Configuration48020. Watchdog Timer (WDT)48120.1 Features48120.2 Overview48120.3 Block Diagram48120.4 Product Dependencies48120.4.1 Power Management48220.4.2 Clocks48220.4.3 Interrupt48220.4.4 Debug Operation48220.4.5 Fuses48220.5 Functional Description48220.5.1 Basic Mode48220.5.1.1 WDT Control Register Access48220.5.1.2 Changing CLK_CNT Clock Source48220.5.1.3 Configuring the WDT48320.5.1.4 Enabling the WDT48320.5.1.5 Clearing the WDT Counter48320.5.1.6 Watchdog Reset48420.5.2 Window Mode48420.5.3 Interrupt Mode48620.5.4 Disabling the WDT48820.5.5 Flash Calibration48820.5.6 Special Considerations48820.5.7 Interrupts48820.6 User Interface48920.6.1 Control Register49020.6.2 Clear Register49220.6.3 Status Register49320.6.4 Interrupt Enable Register49420.6.5 Interrupt Disable Register49520.6.6 Interrupt Mask Register49620.6.7 Interrupt Status Register49720.6.8 Interrupt Clear Register49820.6.9 Version Register49920.7 Module Configuration50021. External Interrupt Controller (EIC)50121.1 Features50121.2 Overview50121.3 Block Diagram50121.4 I/O Lines Description50221.5 Product Dependencies50221.5.1 I/O Lines50221.5.2 Power Management50221.5.3 Clocks50221.5.4 Interrupts50221.5.5 Debug Operation50221.6 Functional Description50221.6.1 External Interrupts50221.6.2 Synchronization and Filtering of External Interrupts50321.6.3 Non-Maskable Interrupt50421.6.4 Asynchronous Interrupts50421.6.5 Wakeup50521.7 User Interface50621.7.1 Interrupt Enable Register50721.7.2 Interrupt Disable Register50821.7.3 Interrupt Mask Register50921.7.4 Interrupt Status Register51021.7.5 Interrupt Clear Register51121.7.6 Mode Register51221.7.7 Edge Register51321.7.8 Level Register51421.7.9 Filter Register51521.7.10 Test Register51621.7.11 Asynchronous Register51721.7.12 Enable Register51821.7.13 Disable Register51921.7.14 Control Register52021.7.15 Version Register52121.8 Module Configuration52222. Frequency Meter (FREQM)52322.1 Features52322.2 Overview52322.3 Block Diagram52322.4 Product Dependencies52322.4.1 Power Management52322.4.2 Clocks52422.4.3 Debug Operation52422.4.4 Interrupts52422.5 Functional Description52422.5.1 Reference Clock52422.5.1.1 Cautionary Note52522.5.2 Measurement52522.5.3 Interrupts52522.6 User Interface52622.6.1 Control Register52722.6.2 Mode Register52822.6.3 Status Register52922.6.4 Value Register53022.6.5 Interrupt Enable Register53122.6.6 Interrupt Disable Register53222.6.7 Interrupt Mask Register53322.6.8 Interrupt Status Register53422.6.9 Interrupt Clear Register53522.6.10 Version Register53622.7 Module Configuration53723. General-Purpose Input/Output Controller (GPIO)53923.1 Features53923.2 Overview53923.3 Block Diagram53923.4 I/O Lines Description54023.5 Product Dependencies54023.5.1 Power Management54023.5.2 Clocks54023.5.3 Interrupts54023.5.4 Peripheral Events54023.5.5 Debug Operation54023.6 Functional Description54123.6.1 Basic Operation54223.6.1.1 Module Configuration54223.6.1.2 Available Features54223.6.1.3 Inputs54223.6.1.4 Output Control54223.6.1.5 Peripheral Muxing54223.6.2 Advanced Operation54323.6.2.1 Peripheral I/O Pin Control54323.6.2.2 Pull-up Resistor, Pull-down Resistor Control54323.6.2.3 Output Pin Timings54323.6.2.4 Pin Output Driver Control54423.6.2.5 Input Schmitt Trigger54423.6.2.6 Interrupts54423.6.2.7 Input Glitch Filter54423.6.2.8 Interrupt Timings54523.6.2.9 Peripheral Events54523.7 User Interface54723.7.1 Access Types54723.7.2 GPIO Enable Register55123.7.3 Peripheral Mux Register 055223.7.4 Peripheral Mux Register 155323.7.5 Peripheral Mux Register 255423.7.6 Output Driver Enable Register55523.7.7 Output Value Register55623.7.8 Pin Value Register55723.7.9 Pull-up Enable Register55823.7.10 Pull-down Enable Register55923.7.11 Interrupt Enable Register56023.7.12 Interrupt Mode Register 056123.7.13 Interrupt Mode Register 156223.7.14 Glitch Filter Enable Register56323.7.15 Interrupt Flag Register56423.7.16 Output Driving Capability Register 056523.7.17 Output Driving Capability Register 156623.7.18 Output Slew Rate Register 056723.7.19 Schmitt Trigger Enable Register56823.7.20 Event Enable Register56923.7.21 Parameter Register57023.7.22 Version Register57123.8 Module Configuration57224. Universal Synchronous Asynchronous Receiver Transmitter (USART)57424.1 Features57424.2 Overview57424.3 Block Diagram57524.4 I/O Lines Description57724.5 Product Dependencies57724.5.1 I/O Lines57724.5.2 Clocks57724.5.3 Interrupts57724.6 Functional Description57824.6.1 USART Operating Modes57824.6.2 Basic Operation57824.6.2.1 Receiver and Transmitter Control57924.6.2.2 Transmitter Operations57924.6.2.3 Asynchronous Receiver58024.6.2.4 Synchronous Receiver58124.6.2.5 Receiver Operations58124.6.3 Other Considerations58224.6.3.1 Parity58224.6.3.2 Multidrop Mode58324.6.3.3 Transmitter Timeguard58324.6.3.4 Receiver Time-out58424.6.3.5 Framing Error58524.6.3.6 Transmit Break58524.6.3.7 Receive Break58624.6.4 Baud Rate Generator58624.6.4.1 Baud Rate in Asynchronous Mode58624.6.4.2 Baud Rate Calculation Example58724.6.4.3 Fractional Baud Rate in Asynchronous Mode58724.6.4.4 Baud Rate in Synchronous and SPI Mode58824.6.5 RS485 Mode58824.6.6 Hardware Handshaking58924.6.7 Modem Mode59024.6.8 ISO7816 Mode59124.6.8.1 ISO7816 Mode Overview59124.6.8.2 Baud Rate in ISO 7816 Mode59124.6.8.3 Protocol T=059324.6.8.4 Protocol T=159324.6.8.5 Receive Error Counter59324.6.8.6 Receive NACK Inhibit59324.6.8.7 Transmit Character Repetition59424.6.8.8 Disable Successive Receive NACK59424.6.9 IrDA Mode59424.6.9.1 IrDA Modulation59524.6.9.2 IrDA Baud Rate59524.6.9.3 IrDA Demodulator59624.6.10 LIN Mode59624.6.10.1 Modes of Operation59724.6.10.2 Receiver and Transmitter Control59724.6.10.3 Baud Rate Configuration59724.6.10.4 Character Transmission and Reception59724.6.10.5 Header Transmission (Master Node Configuration)59724.6.10.6 Header Reception (Slave Node Configuration)59724.6.10.7 Slave Node Synchronization59824.6.10.8 Identifier Parity60024.6.10.9 Node Action60024.6.10.10 LIN Response Data Length60124.6.10.11 Checksum60124.6.10.12 Frame Slot Mode60124.6.10.13 LIN Errors60224.6.11 LIN Frame Handling60324.6.11.1 Master Node Configuration60324.6.11.2 Slave Node Configuration60524.6.12 LIN Frame Handling With The Peripheral DMA Controller60624.6.12.1 Master Node Configuration60624.6.12.2 Slave Node Configuration60724.6.13 Wake-up Request60824.6.14 Bus Idle Time-out60824.6.15 SPI Mode60824.6.15.1 Modes of Operation60924.6.15.2 Baud Rate60924.6.15.3 Data Transfer60924.6.15.4 Receiver and Transmitter Control61124.6.15.5 Character Transmission and Reception61124.6.15.6 Receiver Time-out61124.6.16 Manchester Encoder/Decoder61124.6.16.1 Manchester Encoder61124.6.16.2 Manchester Decoder61324.6.16.3 Radio Interface: Manchester Endec Application61524.6.17 Test Modes61624.6.17.1 Normal Mode61624.6.17.2 Automatic Echo Mode61624.6.17.3 Local Loopback Mode61724.6.17.4 Remote Loopback Mode61724.6.18 Interrupts61724.6.19 Using the Peripheral DMA Controller61924.6.20 Write Protection Registers61924.7 User Interface62124.7.1 Control Register62224.7.2 Mode Register62424.7.3 Interrupt Enable Register62724.7.4 Interrupt Disable Register62824.7.5 Interrupt Mask Register62924.7.6 Channel Status Register63024.7.7 Receiver Holding Register63324.7.8 Transmitter Holding Register63424.7.9 Baud Rate Generator Register63524.7.10 Receiver Time-out Register63724.7.11 Transmitter Timeguard Register63824.7.12 FI DI Ratio Register63924.7.13 Number of Errors Register64024.7.14 IrDA Filter Register64124.7.15 Manchester Configuration Register64224.7.16 LIN Mode Register64424.7.17 LIN Identifier Register64624.7.18 LIN Baud Rate Register64724.7.19 Write Protect Mode Register64824.7.20 Write Protect Status Register64924.7.21 Version Register65024.8 Module Configuration65125. Picopower UART (PICOUART)65225.1 Features65225.2 Overview65225.3 Block Diagram65225.4 I/O Lines Description65325.5 Product Dependencies65325.5.1 I/O Lines65325.5.2 Power Management65325.5.3 Clocks65325.5.4 Backup Power Management65325.5.5 Peripheral Events65325.6 Functional Description65325.6.1 Reception Operation65325.6.2 Wakeup from Power Save Mode65425.6.3 Peripheral Event65425.7 User Interface65625.7.1 Control Register65725.7.2 Configuration Register65825.7.3 Status Register65925.7.4 Receive Holding Register66025.7.5 Version Register66125.8 Module Configuration66226. Serial Peripheral Interface (SPI)66326.1 Features66326.2 Overview66326.3 Block Diagram66426.4 Application Block Diagram66426.5 I/O Lines Description66526.6 Product Dependencies66526.6.1 I/O Lines66526.6.2 Clocks66526.6.3 Interrupts66526.7 Functional Description66526.7.1 Modes of Operation66526.7.2 Data Transfer66626.7.3 Master Mode Operations66726.7.3.1 Master Mode Block Diagram66826.7.3.2 Master Mode Flow Diagram66926.7.3.3 Clock Generation67026.7.3.4 Transfer Delays67026.7.3.5 Peripheral Selection67126.7.3.6 Peripheral Chip Select Decoding67126.7.3.7 Peripheral Deselection67126.7.3.8 FIFO Management67226.7.3.9 Mode Fault Detection67326.7.4 SPI Slave Mode67426.8 User Interface67626.8.1 Control Register67726.8.2 Mode Register67826.8.3 Receive Data Register68026.8.4 Transmit Data Register68126.8.5 Status Register68226.8.6 Interrupt Enable Register68326.8.7 Interrupt Disable Register68426.8.8 Interrupt Mask Register68526.8.9 Chip Select Register 068626.8.10 Chip Select Register 168926.8.11 Chip Select Register 269226.8.12 Chip Select Register 369526.8.13 Write Protection Control Register69826.8.14 Write Protection Status Register69926.8.15 Features Register70026.8.16 Version Register70226.9 Module Configuration70327. Two-wire Master Interface (TWIM)70427.1 Features70427.2 Overview70427.3 List of Abbreviations70527.4 Block Diagram70527.5 Application Block Diagram70627.6 I/O Lines Description70627.7 Product Dependencies70627.7.1 I/O Lines70627.7.2 Power Management70627.7.3 Clocks70727.7.4 DMA70727.7.5 Interrupts70727.7.6 Debug Operation70727.8 Functional Description70827.8.1 Transfer Format70827.8.2 Operation70827.8.2.1 High-speed-mode70927.8.2.2 Clock Generation71027.8.2.3 Setting up and Performing a Transfer71127.8.3 Master Transmitter Mode71227.8.4 Master Receiver Mode71327.8.5 Using the Peripheral DMA Controller71427.8.5.1 Data Transmit with the Peripheral DMA Controller71427.8.5.2 Data Receive with the Peripheral DMA Controller71427.8.6 Multi-master Mode71527.8.7 Combined Transfers71627.8.7.1 Write Followed by Write71627.8.7.2 Read Followed by Read71727.8.7.3 Write Followed by Read71727.8.7.4 Read Followed by Write71727.8.8 Ten Bit Addressing71827.8.8.1 Master Transmitter71827.8.8.2 Master Receiver71827.8.9 SMBus Mode71927.8.9.1 Packet Error Checking71927.8.9.2 Timeouts72027.8.10 Identifying Bus Events72027.9 User Interface72227.9.1 Control Register72327.9.2 Clock Waveform Generator Register72427.9.3 SMBus Timing Register72527.9.4 Command Register72627.9.5 Next Command Register72827.9.6 Receive Holding Register72927.9.7 Transmit Holding Register73027.9.8 Status Register73127.9.9 Interrupt Enable Register73327.9.10 Interrupt Disable Register73427.9.11 Interrupt Mask Register73527.9.12 Status Clear Register73627.9.13 Parameter Register73727.9.14 Version Register73827.9.15 HS-mode Clock Waveform Generator Register73927.9.16 Slew Rate Register74027.9.17 HS-mode Slew Rate Register74127.10 Module Configuration74228. Two-wire Slave Interface (TWIS)74328.1 Features74328.2 Overview74328.3 List of Abbreviations74428.4 Block Diagram74428.5 Application Block Diagram74528.6 I/O Lines Description74528.7 Product Dependencies74528.7.1 I/O Lines74528.7.2 Power Management74528.7.3 Clocks74628.7.4 DMA74628.7.5 Interrupts74628.7.6 Debug Operation74628.8 Functional Description74628.8.1 Transfer Format74628.8.2 Operation74728.8.3 High-speed-mode74728.8.3.1 Bus Timing74828.8.3.2 Setting Up and Performing a Transfer74928.8.3.3 Address Matching74928.8.3.4 Clock Stretching74928.8.3.5 Bus Errors75028.8.4 Slave Transmitter Mode75028.8.5 Slave Receiver Mode75128.8.6 Interactive ACKing Received Data Bytes75228.8.7 Using the Peripheral DMA Controller75328.8.7.1 Data Transmit with the Peripheral DMA Controller75328.8.7.2 Data Receive with the Peripheral DMA Controller75328.8.8 SMBus Mode75328.8.8.1 Packet Error Checking (PEC)75328.8.8.2 Timeouts75428.8.9 Wakeup from Sleep Modes by TWI Address Match75428.8.10 Identifying Bus Events75528.9 User Interface75728.9.1 Control Register75828.9.2 NBYTES Register76028.9.3 Timing Register76128.9.4 Receive Holding Register76228.9.5 Transmit Holding Register76328.9.6 Packet Error Check Register76428.9.7 Status Register76528.9.8 Interrupt Enable Register76728.9.9 Interrupt Disable Register76828.9.10 Interrupt Mask Register76928.9.11 Status Clear Register77028.9.12 Parameter Register77128.9.13 Version Register77228.9.14 HS-mode Timing Register77328.9.15 Slew Rate Register77428.9.16 HS-mode Slew Rate Register77528.10 Module Configuration77629. Inter-IC Sound Controller (IISC)77729.1 Features77729.2 Overview77729.3 Block Diagram77829.4 I/O Lines Description77829.5 Product Dependencies77829.5.1 I/O lines77829.5.2 Power Management77829.5.3 Clocks77929.5.4 DMA77929.5.5 Interrupts77929.5.6 Debug Operation77929.6 Functional Description77929.6.1 Initialization77929.6.2 Basic Operation77929.6.3 Master, Controller, and Slave Modes78029.6.4 I2S Reception and Transmission Sequence78029.6.5 Serial Clock and Word Select Generation78129.6.6 Mono78229.6.7 Holding Registers78229.6.8 DMA Operation78329.6.9 Loop-back Mode78329.6.10 Interrupts78329.7 IISC Application Examples78429.8 User Interface78629.8.1 Control Register78729.8.2 Mode Register78829.8.3 Status Register79029.8.4 Status Clear Register79129.8.5 Status Set Register79229.8.6 Interrupt Enable Register79329.8.7 Interrupt Disable Register79429.8.8 Interrupt Mask Register79529.8.9 Receive Holding Register79629.8.10 Transmit Holding Register79729.8.11 Module Version79829.8.12 Module Parameters79929.9 Module Configuration80030. Timer/Counter (TC)80130.1 Features80130.2 Overview80130.3 Block Diagram80230.4 I/O Lines Description80230.5 Product Dependencies80230.5.1 I/O Lines80230.5.2 Power Management80330.5.3 Clocks80330.5.4 Interrupts80330.5.5 Peripheral Events80330.5.6 Debug Operation80330.6 Functional Description80330.6.1 TC Description80330.6.1.1 Channel I/O Signals80330.6.1.2 16-bit counter80330.6.1.3 Clock selection80430.6.1.4 Clock control80530.6.1.5 TC operating modes80630.6.1.6 Trigger80630.6.1.7 Peripheral events on TIOA/TIOB inputs80730.6.2 Capture Operating Mode80730.6.2.1 Capture registers A and B80730.6.2.2 Trigger conditions80730.6.3 Waveform Operating Mode80930.6.3.1 Waveform selection80930.6.3.2 WAVSEL = 081130.6.3.3 WAVSEL = 281230.6.3.4 WAVSEL = 181330.6.3.5 WAVSEL = 381530.6.3.6 External event/trigger conditions81630.6.3.7 Output controller81630.7 2-bit Gray Up/Down Counter for Stepper Motor81730.8 Write Protection System81730.9 User Interface81830.9.1 Channel Control Register82030.9.2 Channel Mode Register: Capture Mode82130.9.3 Channel Mode Register: Waveform Mode82330.9.4 Stepper Motor Mode Register82730.9.5 Channel Counter Value Register82830.9.6 Channel Register A82930.9.7 Channel Register B83030.9.8 Channel Register C83130.9.9 Channel Status Register83230.9.10 Channel Interrupt Enable Register83430.9.11 Channel Interrupt Disable Register83530.9.12 Channel Interrupt Mask Register83630.9.13 Block Control Register83730.9.14 Block Mode Register83830.9.15 Write Protect Mode Register84030.9.16 Features Register84130.9.17 Version Register84230.10 Module Configuration84331. Peripheral Event Controller (PEVC)84431.1 Features84431.2 Overview84431.3 Block Diagram84531.4 I/O Lines Description84631.5 Product Dependencies84631.5.1 I/O Lines84631.5.2 Power Management and Low Power Operation84631.5.3 Clocks84731.5.4 Interrupts84831.5.5 Debug Operation84831.6 Functional Description84931.6.1 PEVC Channel Operation84931.6.1.1 Channel Setup84931.6.1.2 Channel Operation84931.6.1.3 Software Event84931.6.2 Event Shaper (EVS) Operation85031.6.2.1 Input Glitch Filter (IGF)85031.6.3 Event Propagation Latency85031.7 Application Example85131.8 User Interface85231.8.1 Channel Status Register85331.8.2 Channel Enable Register85431.8.3 Channel Disable Register85531.8.4 Software Event Register85631.8.5 Channel / User Busy85731.8.6 Trigger Interrupt Enable Register85831.8.7 Trigger Interrupt Disable Register85931.8.8 Trigger Interrupt Mask Register86031.8.9 Trigger Status Register86131.8.10 Trigger Status Clear Register86231.8.11 Overrun Interrupt Enable Register86331.8.12 Overrun Interrupt Disable Register86431.8.13 Overrun Interrupt Mask Register86531.8.14 Overrun Status Register86631.8.15 Overrun Status Clear Register86731.8.16 Channel Multiplexer Register86831.8.17 Event Shaper Register86931.8.18 Input Glitch Filter Divider Register87031.8.19 Parameter Register87131.8.20 Version Register87231.9 Module Configuration87332. Audio Bit Stream DAC (ABDACB)87632.1 Features87632.2 Overview87632.3 Block Diagram87632.4 I/O Lines Description87732.5 Product Dependencies87732.5.1 I/O lines87732.5.2 Clocks87732.5.3 DMA87732.5.4 Interrupts87732.6 Functional Description87832.6.1 Construction87832.6.1.1 CIC Interpolation Filter87832.6.1.2 Sigma Delta Modulator87832.6.1.3 Recreating the Analog Signal87832.6.2 Initialization87832.6.3 Basic operation87932.6.4 Data Format87932.6.5 Data Swapping87932.6.6 Common Mode Offset Control87932.6.7 Volume Control88032.6.8 Mono88132.6.9 Alternative Upsampling Ratio88132.6.10 DMA operation88132.6.11 Interrupts88132.6.12 Frequency Response88232.7 User Interface88532.7.1 Control Register88632.7.2 Sample Data Register 088832.7.3 Sample Data Register 188932.7.4 Volume Control Register 089032.7.5 Volume Control Register 189132.7.6 Interrupt Enable Register89232.7.7 Interrupt Disable Register89332.7.8 Interrupt Mask Register89432.7.9 Status Register89532.7.10 Status Clear Register89632.7.11 Parameter Register89732.7.12 Version Register89832.8 Module Configuration89933. Digital to Analog Converter Controller (DACC)90033.1 Features90033.2 Overview90033.3 Block Diagram90133.4 Signal Description90133.5 Product Dependencies90133.5.1 Clocks90133.5.2 Interrupt Sources90233.6 Functional Description90233.6.1 Digital-to-Analog Conversion90233.6.2 Conversion FIFO90233.6.3 Conversion Triggers90233.6.4 Write Protection Registers90333.7 User Interface90433.7.1 Control Register90533.7.2 Mode Register90633.7.3 Conversion Data Register90733.7.4 Interrupt Enable Register90833.7.5 Interrupt Disable Register90933.7.6 Interrupt Mask Register91033.7.7 Interrupt Status Register91133.7.8 Write Protect Mode Register91233.7.9 Write Protect Status Register91333.7.10 Version Register91433.8 Module Configuration91534. Capacitive Touch Module (CATB)91634.1 Features91634.2 Overview91634.3 Block Diagram91734.4 I/O Lines Description91734.5 Product Dependencies91734.5.1 I/O Lines91734.5.2 Power Management91734.5.3 Clocks91734.5.4 Interrupts91834.5.5 Direct Memory Access91834.5.6 Debug Operation91834.6 Functional Description91834.6.1 Principle of Operation91834.6.2 Basic Operation91934.6.3 Differential Mode92034.6.4 Thresholding92034.6.5 Acquisition Clock and Timing92134.6.6 Filter Algorithm92134.6.7 Multiple Sensors and DMA Operation92234.6.8 Spread-Spectrum Operation92534.6.9 Interrupts92534.6.10 Peripheral Event Triggered Operation92534.7 User Interface92734.7.1 Control Register92834.7.2 Counter Control Register93034.7.3 Sensor Idle Level93134.7.4 Sensor Relative Level93234.7.5 Sensor Raw Value93334.7.6 Filter Timing Register93434.7.7 Threshold Register93534.7.8 Pin Selection Register93634.7.9 Direct Memory Access Register93734.7.10 Interrupt Status Register93834.7.11 Interrupt Enable Register93934.7.12 Interrupt Disable Register94034.7.13 Interrupt Mask Register94134.7.14 Status Clear Register94234.7.15 In-Touch Status Register i94334.7.16 In-Touch Status Clear Register n94434.7.17 Out-of-Touch Status Register i94534.7.18 Out of Touch Status Clear Register n94634.7.19 Parameter Register94734.7.20 Version Register94834.8 Module Configuration94935. True Random Number Generator (TRNG)95035.1 Features95035.2 Overview95035.3 Functional Description95035.4 User Interface95135.4.1 Control Register95235.4.2 Interrupt Enable Register95335.4.3 Interrupt Disable Register95435.4.4 Interrupt Mask Register95535.4.5 Interrupt Status Register95635.4.6 Output Data Register95735.4.7 Version Register95835.5 Module Configuration95936. Glue Logic Controller (GLOC)96036.1 Features96036.2 Overview96036.3 Block Diagram96036.4 I/O Lines Description96136.5 Product Dependencies96136.5.1 I/O Lines96136.5.2 Clocks96136.5.3 Debug Operation96136.6 Functional Description96136.6.1 Enabling the Lookup Table Inputs96136.6.2 Configuring the Lookup Table96236.6.3 Output Filter96236.7 User Interface96336.7.1 Control Register n96436.7.2 Truth Table Register n96536.7.3 Parameter Register96636.7.4 Version Register96736.8 Module Configuration96837. Analog Comparator Interface (ACIFC)96937.1 Features96937.2 Overview96937.3 Block Diagram97037.4 I/O Lines Description97037.5 Product Dependencies97137.5.1 I/O Lines97137.5.2 Power Management97137.5.3 Clocks97137.5.4 Interrupts97137.5.5 Peripheral Events97137.5.6 Debug Operation97137.6 Functional Description97137.6.1 Analog Comparator Operation97237.6.1.1 Continuous Measurement Mode97237.6.1.2 User Triggered Single Measurement Mode97237.6.1.3 Peripheral Event Triggered Single Measurement Mode97237.6.1.4 Selecting Comparator Inputs97337.6.2 Interrupt Generation97337.6.3 Peripheral Event Generation97337.6.4 Normal Mode97337.6.4.1 Normal Mode Output97337.6.4.2 Normal Mode Interrupt97337.6.4.3 Normal Mode Peripheral Events97437.6.5 Window Mode97437.6.5.1 Window Mode Output97537.6.5.2 Window Mode Interrupts97537.6.5.3 Window Mode Peripheral Events97637.6.6 Analog Hysteresis Control97637.6.7 Power Dissipation and Speed Trade-off97737.6.8 Wake Up from Sleep Modes by Interrupt97737.7 Peripheral Event Triggers97737.8 AC Test mode97737.9 User Interface97837.9.1 Control Register97937.9.2 Status Register98037.9.3 Interrupt Enable Register98137.9.4 Interrupt Disable Register98237.9.5 Interrupt Mask Register98337.9.6 Interrupt Status Register98437.9.7 Interrupt Status Clear Register98537.9.8 Test Register98637.9.9 Parameter Register98737.9.10 Version Register98837.9.11 Windowx Configuration Register98937.9.12 ACx Configuration Register99137.10 Module configuration99338. ADC Interface (ADCIFE)99438.1 Features99438.2 Overview99438.3 Block diagram99538.4 I/O Lines Description99538.5 Product dependencies99538.5.1 I/O Lines99538.5.2 Power Management99638.5.3 Clocks99638.5.4 Interrupt Controller99638.5.5 Event System99638.6 Section 42. ”Electrical Characteristics” on page 1120Functional Description99638.6.1 Initializing the ADCIFE99638.6.2 Basic Operation99738.6.3 ADC Resolution99738.6.4 Differential and Single-Ended Conversion Modes99738.6.5 ADC Clock Configuration99838.6.6 Power Reduction Mode99838.6.7 Power-up and Startup Time99838.6.8 Operation Start/Stop99838.6.9 Analog Reference99938.6.10 GAIN99938.6.11 Conversion Results99938.6.12 Operating Modes Overview99938.6.13 Sequencer Trigger Event (STRIG)100038.6.14 Internal Timer100038.6.15 Peripheral DMA Controller (PDCA) Capability100138.6.16 Zoom Mode100238.6.17 Window Monitor100238.6.18 Interrupts100338.6.19 Conversion Performances100338.7 User Interface100438.7.1 Control Register100538.7.2 Configuration Register100738.7.3 Status Register100938.7.4 Status Clear Register101138.7.5 Sequencer Configuration Register101238.7.6 Configuration Direct Memory Access101738.7.7 Timing Configuration Register101938.7.8 Internal Timer Register102038.7.9 Window Monitor Configuration102138.7.10 Window Monitor Threshold Configuration102238.7.11 Sequencer Last Converted Value102338.7.12 Interrupt Enable Register102438.7.13 Interrupt Disable Register102538.7.14 Interrupt Mask Register102638.7.15 Calibration Register102738.7.16 Module Version102938.7.17 Parameter Register103038.8 Module Configuration103139. LCD Controller (LCDCA)103239.1 Features103239.2 Overview103239.3 Block Diagram103339.4 I/O Lines Description103339.5 Product Dependencies103339.5.1 I/O Lines103439.5.2 Power Management103439.5.3 Clocks103439.5.4 Interrupts103439.5.5 Wake Up103439.5.6 Debug Operation103439.6 Functional Description103439.6.1 LCD Display103439.6.2 Operating modes103539.6.2.1 Static Duty and Static Bias103539.6.2.2 1/2 Duty and 1/3 Bias103639.6.2.3 1/3 Duty and 1/3 Bias103639.6.2.4 1/4 Duty and 1/3 Bias103739.6.3 Enabling/Disabling LCDCA103739.6.4 Waveform Modes103839.6.5 Timing Generation103839.6.5.1 Frame Rate103839.6.5.2 Frame Counters103939.6.6 CPU Display Memory Access104039.6.6.1 Direct Access104039.6.6.2 Indirect Access104039.6.7 Locking Shadow Display Memory104039.6.8 Blinking Modes104039.6.8.1 Software Blinking104039.6.8.2 Hardware Blinking104039.6.9 Autonomous Segment Animation104139.6.10 ASCII Character Mapping104239.6.11 Automated Character Mapping104739.6.11.1 Sequential Characters String Display104739.6.11.2 Scrolling of Characters String104839.6.12 Automated Bit Mapping104939.6.13 Contrast Adjustment105039.6.14 Interrupts105039.6.15 LCD Wake Up105039.6.16 LCD Power Supply105139.7 User Interface105339.7.1 Control Register105439.7.2 Configuration Register105639.7.3 Timing Register105839.7.4 Status Register105939.7.5 Status Clear Register106039.7.6 Data Register Low106139.7.7 Data Register High106239.7.8 Indirect Access Data Register106339.7.9 Blink Configuration Register106439.7.10 Circular Shift Register Configuration106539.7.11 Character Mapping Configuration Register106639.7.12 Character Mapping Data Register106739.7.13 Automated Character Mapping Configuration Register106839.7.14 Automated Character Mapping Data Register107039.7.15 Automated Bit Mapping Configuration Register107139.7.16 Automated Bit Mapping Data Register107239.7.17 Interrupt Enable Register107339.7.18 Interrupt Disable Register107439.7.19 Interrupt Mask Register107539.7.20 Module Version107639.8 Module Configuration107740. Parallel Capture (PARC)108040.1 Features108040.2 Overview108040.3 Block Diagram108040.4 I/O Lines Description108040.5 Product Dependencies108040.5.1 I/O Lines108140.5.2 Power Management108140.5.3 Clocks108140.5.4 DMA108140.5.5 Interrupt108140.5.6 Peripheral Events108140.6 Functional Description108140.6.1 Capture Operation108140.6.2 Peripheral DMA108240.6.3 Peripheral Events108240.6.4 Interrupt Generation108240.7 User Interface108440.7.1 Configuration Register108540.7.2 Control Register108740.7.3 Interrupt Enable Register108840.7.4 Interrupt Disable Register108940.7.5 Interrupt Mask Register109040.7.6 Status Register109140.7.7 Interrupt Status Clear Register109240.7.8 Receive Holding Register109340.7.9 Version Register109440.8 Module Configuration109541. Cyclic Redundancy Check Calculation Unit (CRCCU)109641.1 Features109641.2 Overview109641.3 Block Diagram109641.4 Product Dependencies109641.4.1 Power Management109641.4.2 Clocks109641.4.3 Interrupts109641.4.4 Debug Operation109641.5 Functional Description109741.6 User Interface109941.6.1 Descriptor Base Address Register110041.6.2 DMA Enable Register110141.6.3 DMA Disable Register110241.6.4 DMA Status Register110341.6.5 DMA Interrupt Enable Register110441.6.6 DMA Interrupt Disable Register110541.6.7 DMA Interrupt Mask Register110641.6.8 DMA Interrupt Status Register110741.6.9 Control Register110841.6.10 Mode Register110941.6.11 Status Register111041.6.12 Interrupt Enable Register111141.6.13 Interrupt Disable Register111241.6.14 Interrupt Mask Register111341.6.15 Interrupt Status Register111441.6.16 Version Register111541.6.17 Transfer Address Register111641.6.18 Transfer Control Register111741.6.19 Transfer Reference Register111841.7 Module Configuration111942. Electrical Characteristics112042.1 Absolute Maximum Ratings*112042.2 Operating Conditions112042.3 Supply Characteristics112042.4 Maximum Clock Frequencies112242.5 Power Consumption112442.5.1 Power Scaling 0 and 2112442.5.2 Power Scaling 1112642.5.3 Peripheral Power Consumption in Power Scaling mode 0 and 2113142.5.4 .Peripheral Power Consumption in Power Scaling mode 1113242.6 I/O Pin Characteristics113542.6.1 Normal I/O Pin113542.6.2 High-drive I/O Pin : PA02, PC04, PC05, PC06113642.6.3 USB I/O Pin : PA25, PA26113742.6.4 TWI Pin : PA21, PA22, PA23, PA24, PB14, PB15113742.6.5 High Drive TWI Pin : PB00, PB01114042.7 Oscillator Characteristics114242.7.1 Oscillator 0 (OSC0) Characteristics114242.7.1.1 Digital Clock Characteristics114242.7.1.2 Crystal Oscillator Characteristics114242.7.2 32 kHz Crystal Oscillator (OSC32K) Characteristics114442.7.3 Phase Locked Loop (PLL) Characteristics114542.7.4 Digital Frequency Locked Loop (DFLL) Characteristics114542.7.5 32 kHz RC Oscillator (RC32K) Characteristics114642.7.6 System RC Oscillator (RCSYS) Characteristics114642.7.7 1MHz RC Oscillator (RC1M) Characteristics114742.7.8 4/8/12MHz RC Oscillator (RCFAST) Characteristics114742.7.9 80MHz RC Oscillator (RC80M) Characteristics114842.8 Flash Characteristics114842.9 Analog Characteristics115042.9.1 Voltage Regulator Characteristics115042.9.2 Power-on Reset 33 Characteristics115242.9.3 Brown Out Detectors Characteristics115242.9.4 Analog- to Digital Converter Characteristics115442.9.4.1 Inputs and Sample and Hold Acquisition Times115742.9.5 Digital to Analog Converter Characteristics115842.9.6 Analog Comparator Characteristics115842.9.7 Liquid Crystal Display Controler characteristics116042.9.7.1 Liquid Crystal Controler supply current116042.10 Timing Characteristics116142.10.1 RESET_N Timing116142.10.2 USART in SPI Mode Timing116142.10.2.1 Master mode116142.10.2.2 Slave mode116342.10.3 SPI Timing116742.10.3.1 Master mode116742.10.3.2 Slave mode116842.10.4 TWIM/TWIS Timing117042.10.5 JTAG Timing117142.10.6 SWD Timing117243. Mechanical Characteristics117443.1 Thermal Considerations117443.1.1 Thermal Data117443.1.2 Junction Temperature117443.2 Package Drawings117543.3 Soldering Profile118444. Ordering Information118545. Errata118845.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A118845.1.1 General118845.1.2 SCIF118845.1.3 WDT118845.1.4 SPI118845.1.5 TC118945.1.6 USBC118945.1.7 FLASHCALW119046. Datasheet Revision History119146.1 Rev. A – 09/12119146.2 Rev. B – 10/12119146.3 Rev. C – 02/13119146.4 Rev. D – 03/13119146.5 Rev. E – 07/131192Table of Contents1193Size: 13.4 MBPages: 1204Language: EnglishOpen manual