Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
109
42023E–SAM–07/2013
ATSAM4L8/L4/L2
10.4
I/O Lines Description
10.5
Product Dependencies
10.5.1
Interrupt
The PM interrupt line is connected to one of the internal sources of the NVIC. Using the PM
interrupt requires the NVIC to be programmed first.
interrupt requires the NVIC to be programmed first.
10.5.2
Clock Implementation
In ATSAM4L, the AHB shares the source clock with the CPU.
The clock for the PM bus interface (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. If disabled, it can only be re-
enabled by a reset.
enabled at reset, and can be disabled in the Power Manager. If disabled, it can only be re-
enabled by a reset.
10.6
Functional Description
10.6.1
Synchronous Clocks
The System RC Oscillator (RCSYS) or a set of other clock sources provide the source for the
main clock, which is the common root for the synchronous clocks for the CPU, AHB and APBx
modules. For details about the other main clock sources, refer to the register description of the
Main Clock Control Register (MCCTRL). The main clock is divided by an 8-bit prescaler, and
each of these synchronous clocks can run from any tapping of this prescaler, or the undivided
main clock, as long as f
main clock, which is the common root for the synchronous clocks for the CPU, AHB and APBx
modules. For details about the other main clock sources, refer to the register description of the
Main Clock Control Register (MCCTRL). The main clock is divided by an 8-bit prescaler, and
each of these synchronous clocks can run from any tapping of this prescaler, or the undivided
main clock, as long as f
CPU
≥
f
APBx,
. The synchronous clock source can be changed on-the fly,
responding to varying load in the application. The clocks for each module in each synchronous
clock domain can be individually masked, to avoid power consumption in inactive modules.
Depending on the Power Save mode, some clock domains can be cut.
clock domain can be individually masked, to avoid power consumption in inactive modules.
Depending on the Power Save mode, some clock domains can be cut.
Table 10-1.
I/O Lines Description
Name Description
Type
Active
Level
RESET_N
Reset
Input
Low