Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

Name: CPUMASK/HSBMASK/PBAMASK/PBBMASK/PBCMASK/PBDMASK

Read/Write

Offset: 0x020-0x034

0x00000001/0x000001E2/0x00000000/0x00000001/0x0000001F/0x0000003F-

If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current 

power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is 

shown in 

. After reset, some modules are enabled by default (shown as gray cell).

31

30

29

28

27

26

25

24

MASK[31:24]

23

22

21

20

19

18

17

16

MASK[23:16]

15

14

13

12

11

10

9

8

MASK[15:8]

7

6

5

4

3

2

1

0

MASK[7:0]

Maskable Module Clocks in ATSAM4L.

0

OCD

PDCA

IISC

FLASHCALW

PM

BPM

1

-

FLASHCALW

SPI

HRAMC1

CHIPID

BSCIF

2

-

HRAMC1 

(picoCache RAM)

TC0

HMATRIX

SCIF

AST

3

-

USBC

TC1

PDCA

FREQM

WDT

4

-

CRCCU

TWIM0

CRCCU

GPIO

EIC

5

-

APBA bridge

TWIS0

USBC

PICOUART

6

-

APBB bridge

TWIM1

PEVC

-

7

-

APBC bridge

TWIS1

-

-

8

-

APBD bridge

USART0

-

-

9

-

AESA

USART1

-

-

10

-

-

USART2

-

-

11

-

-

USART3

-

-

12

-

-

ADCIFE

-

-

-