Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
207
42023E–SAM–07/2013
ATSAM4L8/L4/L2
13.6.3.1
Enabling the DFLL
DFLLx is enabled by writing a one to the Enable bit in the DFLLx Configuration Register (DFLLx-
CONF.EN). No other bits or fields in DFLLxCONF must be changed simultaneously, or before
DFLLx is enabled.
CONF.EN). No other bits or fields in DFLLxCONF must be changed simultaneously, or before
DFLLx is enabled.
13.6.3.2
Internal Synchronization
Due to multiple clock domains, values in the DFLLx configuration registers need to be synchro-
nized to other clock domains. The status of this synchronization can be read from the Power and
Clocks Status Register (PCLKSR). Before writing to any of the DFLLx configuration registers,
the user must check that the DFLLx Ready bit in PCLKSR is one (PCLKSR.DFLLxRDY). When
this bit is set, the DFLLx can be configured, and CLK_DFLLx is ready to be used. Any write to
any of the DFLLx configuration register while DFLLxRDY is zero will be ignored. An interrupt can
be generated on a zero-to-one transition of DFLLxRDY.
nized to other clock domains. The status of this synchronization can be read from the Power and
Clocks Status Register (PCLKSR). Before writing to any of the DFLLx configuration registers,
the user must check that the DFLLx Ready bit in PCLKSR is one (PCLKSR.DFLLxRDY). When
this bit is set, the DFLLx can be configured, and CLK_DFLLx is ready to be used. Any write to
any of the DFLLx configuration register while DFLLxRDY is zero will be ignored. An interrupt can
be generated on a zero-to-one transition of DFLLxRDY.
Before reading the value in any of the DFLLx configuration registers a one must be written to the
Synchronization bit in the DFLLx Synchronization Register (DFLLxSYNC.SYNC). The DFLLx
configuration registers are ready to be read when PCLKSR.DFLLxRDY is set.
Synchronization bit in the DFLLx Synchronization Register (DFLLxSYNC.SYNC). The DFLLx
configuration registers are ready to be read when PCLKSR.DFLLxRDY is set.
13.6.3.3
Disabling the DFLL
DFLLx is disabled by writing a zero to DFLLxCONF.EN. No other bits or fields in DFLLxCONF
must be changed simultaneously.
must be changed simultaneously.
13.6.3.4
Open Loop Operation
After enabling DFLLx, open loop mode is selected. When operating in open loop mode the out-
put frequency of the DFLLx will be determined by the values written to the Calibration Value field
and the Range Value field in DFLLxCONF (DFLLxCONF.CALIB and DFLLxCONF.RANGE), and
the Coarse Value field and the Fine Value field in the DFLLx Value Register (DFLLxVAL.COARS
and DFLLxVAL.FINE). CALIB is used for process calibration, and should not be changed by the
user. It is loaded with a factory defined value stored in the Flash fuses. The Fuse Calibration
Done bit in DFLLxCONF (DFLLXCONF.FCD) is set when the fuse values are loaded. Writing a
zero to this bit will reload the CALIB value from the Flash fuses after any reset. Refer to the Fuse
Settings chapter for more details about how to program the fuses. RANGE selects the frequency
range of the DFLLx, see
put frequency of the DFLLx will be determined by the values written to the Calibration Value field
and the Range Value field in DFLLxCONF (DFLLxCONF.CALIB and DFLLxCONF.RANGE), and
the Coarse Value field and the Fine Value field in the DFLLx Value Register (DFLLxVAL.COARS
and DFLLxVAL.FINE). CALIB is used for process calibration, and should not be changed by the
user. It is loaded with a factory defined value stored in the Flash fuses. The Fuse Calibration
Done bit in DFLLxCONF (DFLLXCONF.FCD) is set when the fuse values are loaded. Writing a
zero to this bit will reload the CALIB value from the Flash fuses after any reset. Refer to the Fuse
Settings chapter for more details about how to program the fuses. RANGE selects the frequency
range of the DFLLx, see
.
It is possible to change the value of DFLLxCONF.CALIB, DFLLxCONF.RANGE, DFLLx-
VAL.COARSE, and DFLLxVAL.FINE, and thereby the output frequency of the DFLLx output
clock, CLK_DFLLx, while the DFLL is enabled and in use.
VAL.COARSE, and DFLLxVAL.FINE, and thereby the output frequency of the DFLLx output
clock, CLK_DFLLx, while the DFLL is enabled and in use.
CLK_DFLLx is ready to be used when PCLKSR.DFLLxRDY is set after enabling the DFLLx.
The frequency range in open loop mode is 20-150MHz, but maximum frequency can be higher,
and the minimum frequency can be lower. The best way to start the DFLL at a specific frequency
and the minimum frequency can be lower. The best way to start the DFLL at a specific frequency
Table 13-2.
DFLL Frequency Range
RANGE
Frequency range [MHz]
0
96-150
1
50-110
2
25-55
3
20-30