Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

Note:

1. See 

The JTAG pins switch to the JTAG functions if a rising edge is detected on TCK low after the
RESET_N pin has been released. The TMS, and TDI pins have pull-up resistors when used as
JTAG pins. The TCK pin always has pull-up enabled during reset. The JTAG pins can be used
as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Refer to 

 for the JTAG port connections.

For more details, refer to 

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and-
inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the
pins have the same characteristics as GPIO pins.

All the I/O lines integrate a pull-up/pull-down resistor and slew rate controller

. Programming

these features is performed independently for each I/O line through the GPIO Controllers. After
reset, I/O lines default as inputs with pull-up and pull-down resistors disabled and slew rate
enabled. 

The six pins PA02, PB00, PB01, PC04, PC05 and PC06 have high-drive output capabilities.
Refer to 

 for electri-

cal characteristics.

When these pins are used for USB, the pins are behaving according to the USB specification.
When used as GPIO pins or used for other peripherals, the pins have the same behavior as
other normal I/O pins, but the characteristics are different. Refer to 

 for electrical characteristics.

These pins are compliant to USB standard only when VDDIO power supply is 3.3

V

 nominal.

PA31 - PA00

Parallel I/O Controller I/O Port A

I/O

PB15 - PB00

Parallel I/O Controller I/O Port B

I/O

PC31 - PC00

Parallel I/O Controller I/O Port C

I/O

Signal Descriptions List (Sheet 4 of 4)