Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
340
42023E–SAM–07/2013
ATSAM4L8/L4/L2
17. USB Device and Embedded Host Interface (USBC)
Rev: 3.1.0.19
17.1
Features
•
Compatible with the USB 2.0 specification
•
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
•
Supports Embedded Host
•
8 physical pipes/endpoints in ping-pong mode
•
Flexible pipe/endpoint configuration and reallocation of data buffers in embedded RAM
•
Supports an endpoint numbering range from 0 to 15, in both I/O directions
•
Supports an infinite number of virtual pipes (alternate pipe)
•
Up to two memory banks per pipe/endpoint
•
Built-in DMA with multi-packet support through ping-pong mode
•
On-chip transceivers with built-in pull-ups and pull-downs
•
On-chip Embedded Host pad with a VBUS analog comparator
17.2
Overview
The Universal Serial Bus interface (USBC) module complies with the Universal Serial Bus (USB)
2.0 specification supporting both the device and the embedded host mode.
2.0 specification supporting both the device and the embedded host mode.
Each pipe/endpoint can be configured into one of several transfer types. It can be associated
with one or more memory banks (located inside the embedded system or CPU RAM) used to
store the current data payload. If two banks are used (“ping-pong” mode), then one bank is read
or written by the CPU (or any other AHB master) while the other is read or written by the USBC
core.
with one or more memory banks (located inside the embedded system or CPU RAM) used to
store the current data payload. If two banks are used (“ping-pong” mode), then one bank is read
or written by the CPU (or any other AHB master) while the other is read or written by the USBC
core.
describes the hardware configuration of the USBC module.
17.3
Block Diagram
The USBC interfaces a USB link with a data flow stored in the embedded ram (CPU or AHB).
The USBC requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock. For
more details see
more details see
. The 48MHz clock is used to generate either a 12MHz
full-speed or a 1.5MHz low-speed bit clock from the received USB differential data, and to trans-
mit data according to full- or low-speed USB device tolerances. Clock recovery is achieved by a
digital phase-locked loop (a DPLL, not represented) in the USBC module, which complies with
the USB jitter specifications.
mit data according to full- or low-speed USB device tolerances. Clock recovery is achieved by a
digital phase-locked loop (a DPLL, not represented) in the USBC module, which complies with
the USB jitter specifications.
Table 17-1.
Description of USB pipes/endpoints
pipe/endpoint
Mnemonic
Max. size
Number of
available banks
Type
0
PEP0
1023 bytes
1
Control/Isochronous/Bulk/Interrupt
1
PEP1
1023 bytes
2
Control/Isochronous/Bulk/Interrupt
2
PEP2
1023 bytes
2
Control/Isochronous/Bulk/Interrupt
...
...
...
...
...
7
PEP7
1023 bytes
2
Control/Isochronous/Bulk/Interrupt