Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
353
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 17-7. Control Write
• Control read
shows a control read transaction. The USBC has to manage the simul-
taneous write requests from the CPU and USB host.
Figure 17-8. Control Read
A NAK handshake is always generated as the first status stage command. The UESTAn.NAKINI
bit is set. It allows the user to know that the host aborts the IN data stage. As a consequence,
the user should stop processing the IN data stage and should prepare to receive the OUT status
stage by checking the UESTAn.RXOUTI bit.
bit is set. It allows the user to know that the host aborts the IN data stage. As a consequence,
the user should stop processing the IN data stage and should prepare to receive the OUT status
stage by checking the UESTAn.RXOUTI bit.
The OUT retry is always ACKed. This OUT reception sets RXOUTI. Handle this with the follow-
ing software algorithm:
ing software algorithm:
// process the IN data stage
set TXINI
wait for RXOUTI (rising) OR TXINI (falling)
if RXOUTI is high, then process the OUT status stage
if TXINI is low, then return to process the IN data stage
Once the OUT status stage has been received, the USBC waits for a SETUP request. The
SETUP request has priority over all other requests and will be ACKed.
SETUP request has priority over all other requests and will be ACKed.
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW
SW
OUT
HW
SW
OUT
HW
SW
IN
IN
NAK
SW
DATA
SETUP
STATUS
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW
SW
IN
HW
SW
IN
OUT
OUT
NAK
SW
SW
HW
Wr Enable
HOST
HOST
Wr Enable
CPU
CPU
DATA
SETUP
STATUS