Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

UECONn, n in [0..7]

Read-Only

0x01C0 + (n * 0x04)

0x00000000

This bit is cleared when the BUSY0C bit is written to one.

This bit is set when the BUSY0ES bit is written to one. This will set the bank 0 as “busy”. All transactions, except SETUP, 

destined to this bank will be rejected (i.e: NAK token will be answered).

This bit is cleared when the BUSY1C bit is written to one.

This bit is set when the BUSY1ES bit is written to one. This will set the bank 1 as “busy”. All transactions, except SETUP, 

destined to this bank will be rejected (i.e: NAK token will be answered).

This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.

This bit is set when the STALLRQS bit is written to one, requesting a STALL handshake to be sent to the host.

The data toggle sequence is cleared when the RSTDTS bit is written to one (i.e., Data0 data toggle sequence will be selected 

for the next sent (IN endpoints) or received (OUT endpoints) packet.

This bit is always read as zero.

For control endpoints:

The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them for these endpoints. When read, 

their value is always 0.

For IN endpoints:

This bit is cleared when the FIFOCONC bit is written to one, sending the FIFO data and switching to the next bank.

This bit is set simultaneously to TXINI, when the current bank is free.

For OUT endpoints:

This bit is cleared when the FIFOCONC bit is written to one, freeing the current bank and switching to the next.

This bit is set simultaneously to RXINI, when the current bank is full.

31

30

29

28

27

26

25

24

-

-

-

-

-

-

BUSY1E

BUSY0E

23

22

21

20

19

18

17

16

-

-

-

-

STALLRQ

RSTDT

-

-

15

14

13

12

11

10

9

8

-

FIFOCON

KILLBK

NBUSYBKE

RAMACERE

-

-

NREPLY

7

6

5

4

3

2

1

0

-

STALLEDE/

CRCERRE

-

NAKINE

NAKOUTE

RXSTPE/

ERRORFE

RXOUTE

TXINE