Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

UHINT

Read-Only

0x0404

0x00000000

Note:

1. PnINT bits are within the range from P0INT to P7INT.

This bit is cleared when the interrupt source is served. 

This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe 

interrupt enable bit is one (UHINTE register). 

This bit is cleared when the HWUPIC bit is written to one.

This bit is set when:

- the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is detected.

- the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.

- the host controller is in the operationnal state (VBUSRQ is one) and a device connection is detected.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

This bit is cleared when the HSOFIC bit is written to one.

This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the 

host controller in low speed mode, this bit is also set when a keep-alive is sent.

This bit is set when an Upstream Resume has been received from the Device.

This bit is cleared when the RXRSMIC is written to one.

This bit is cleared when the RSMEDIC bit is written to one.

This bit set when a Downstream Resume has been sent to the Device.

This bit is cleared when the RSTIC bit is written to one.

This bit is set when a USB Reset has been sent to the device.

This bit is cleared when the DDISCIC bit is written to one.

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

-

-

-

-

-

-

-

P8INT

15

14

13

12

11

10

9

8

P6INT

P4INT

P3INT

P1INT

P0INT

7

6

5

4

3

2

1

0

-

HWUPI

HSOFI

RXRSMI

RSMEDI

RSTI

DDISCI

DCONNI