Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

Finally, AESA supports several hardware countermeasures that are useful for protecting data
against differential power analysis attacks (

In order to use this module, other parts of the system must be configured correctly, as described
below.

If the CPU enters a sleep mode that disables clocks used by AESA, the module will stop func-
tioning and resume operation after the system wakes up from sleep mode.

The clock (CLK_AESA) for AESA’s core operations (such as encryption and decryption) is a
generic clock (GCLK). It is recommended that AESA be disabled before CLK_AESA is disabled
to avoid freezing the module in an undefined state.

The AESA interrupt request line is connected to the NVIC. Using the AESA interrupt requires the
NVIC to be programmed first.

AESA must be enabled before it can be programmed or used. It is enabled by writing a one to
the Enable Module (ENABLE) bit in the Control (CTRL) register. The module is disabled by writ-
ing a zero to the same bit.

AESA supports both the encryption and decryption of data. The desired mode of data process-
ing is selected by programming the Encryption (ENCRYPT) bit in the MODE register.

The 128-bit key is written to the four 32-bit KEY registers. Note that access to the KEY registers
is by 32-bit words only (i.e., no halfword or byte access).

Core

High Speed Bus 

Slave

High Speed Bus

DMA Controller

AESA

DMA 

Controller 
Hardware 

Handshaking 

Interface

CLK_AESA

CLK_HSB

Interrupt 

Controller

IRQ

Figure 18-1. AESA Block Diagram