Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

If ADD is ‘1’, the prescaler frequency is increased:

Note that for these formulas to be within an error of 0.01%, it is recommended that the prescaler
bit that is used as the clock for the counter (selected by CR.PSEL) or to trigger the periodic inter-
rupt (selected by PIRn.INSEL) be bit 6 or higher.

As the prescaler and counter operate asynchronously from the user interface, the AST needs a
few clock cycles to synchronize the values written to the CR, CV, SCR, WER, EVE, EVD, PIRn,
ARn, and DTR registers. The Busy bit in the Status Register (SR.BUSY) indicates that the syn-
chronization is ongoing. During this time, writes to these registers will be discarded and reading
will return a zero value. 

Note that synchronization takes place also if the prescaler is clocked from CLK_AST.

0

1

1

roundup

256

--------------------

⎝

⎠

⎛

⎞

2

(

)

⋅

1

–

--------------------------------------------------------------------------------

+

⎝

⎠

⎜

⎟

⎜

⎟

⎜

⎟

⎛

⎞

=