Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
579
42023E–SAM–07/2013
ATSAM4L8/L4/L2
4.
Check that CSR.TXRDY and/or CSR.RXRDY is one before writing to THR and/or read-
ing from RHR respectively
ing from RHR respectively
24.6.2.1
Receiver and Transmitter Control
After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to
the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN)
respectively. They may be enabled together and can be configured both before and after they
have been enabled. The user can reset the USART receiver/transmitter at any time by writing a
one to the Reset Receiver/Reset Transmitter bit (CR.RSTRX/CR.RSTTX) respectively. This
software reset clears status bits and resets internal state machines, immediately halting any
communication. The user interface configuration registers will retain their values.
the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN)
respectively. They may be enabled together and can be configured both before and after they
have been enabled. The user can reset the USART receiver/transmitter at any time by writing a
one to the Reset Receiver/Reset Transmitter bit (CR.RSTRX/CR.RSTTX) respectively. This
software reset clears status bits and resets internal state machines, immediately halting any
communication. The user interface configuration registers will retain their values.
The user can disable the receiver/transmitter by writing a one to either the Receiver Disable, or
Transmitter Disable bit (CR.RXDIS, or CR.TXDIS). If the receiver is disabled during a character
reception, the USART will wait for the current character to be received before disabling. If the
transmitter is disabled during transmission, the USART will wait until both the current character
and the character stored in the Transmitter Holding Register (THR) are transmitted before dis-
abling. If a timeguard has been implemented it will remain functional during the transmission.
Transmitter Disable bit (CR.RXDIS, or CR.TXDIS). If the receiver is disabled during a character
reception, the USART will wait for the current character to be received before disabling. If the
transmitter is disabled during transmission, the USART will wait until both the current character
and the character stored in the Transmitter Holding Register (THR) are transmitted before dis-
abling. If a timeguard has been implemented it will remain functional during the transmission.
24.6.2.2
Transmitter Operations
The transmitter operates equally in both Synchronous and Asynchronous operating modes
(MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are
successively shifted out on the TXD pin at each falling edge of the serial clock. The number of
data bits is selected by the Character Length field (MR.CHRL) and the 9-bit Character Length bit
in the Mode Register (MR.MODE9). Nine bits are selected by writing a one to MR.MODE9, over-
riding any value in MR.CHRL. The parity bit configuration is selected in the MR.PAR field. The
Most Significant Bit First bit (MR.MSBF) selects which data bit to send first. The number of stop
bits is selected by the MR.NBSTOP field. The 1.5 stop bit configuration is only supported in
asynchronous mode.
(MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are
successively shifted out on the TXD pin at each falling edge of the serial clock. The number of
data bits is selected by the Character Length field (MR.CHRL) and the 9-bit Character Length bit
in the Mode Register (MR.MODE9). Nine bits are selected by writing a one to MR.MODE9, over-
riding any value in MR.CHRL. The parity bit configuration is selected in the MR.PAR field. The
Most Significant Bit First bit (MR.MSBF) selects which data bit to send first. The number of stop
bits is selected by the MR.NBSTOP field. The 1.5 stop bit configuration is only supported in
asynchronous mode.
Figure 24-3. Character Transmit
The characters are sent by writing to the Character to be Transmitted field (THR.TXCHR). The
transmitter status can be read from the Transmitter Ready and Transmitter Empty bits in the
Channel Status Register (CSR.TXRDY/CSR.TXEMPTY). CSR.TXRDY is set when THR is
empty. CSR.TXEMPTY is set when both THR and the transmit shift register are empty (trans-
mission complete). An interrupt request is generated if the corresponding bit in the Interrupt
Mask Register (IMR) is set (IMR.TX RDY/IMR.TXEM PTY). Both CSR.TXRDY and
CSR.TXEMPTY are cleared when the transmitter is disabled. CSR.TXRDY and CSR.TXEMPY
can also be cleared by writing a one to the Start Break bit in CR (CR.STTBRK). Writing a char-
acter to THR while CSR.TXRDY is zero has no effect and the written character will be lost.
transmitter status can be read from the Transmitter Ready and Transmitter Empty bits in the
Channel Status Register (CSR.TXRDY/CSR.TXEMPTY). CSR.TXRDY is set when THR is
empty. CSR.TXEMPTY is set when both THR and the transmit shift register are empty (trans-
mission complete). An interrupt request is generated if the corresponding bit in the Interrupt
Mask Register (IMR) is set (IMR.TX RDY/IMR.TXEM PTY). Both CSR.TXRDY and
CSR.TXEMPTY are cleared when the transmitter is disabled. CSR.TXRDY and CSR.TXEMPY
can also be cleared by writing a one to the Start Break bit in CR (CR.STTBRK). Writing a char-
acter to THR while CSR.TXRDY is zero has no effect and the written character will be lost.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock