Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

A START condition is transmitted and master transmitter mode is initiated when the bus is free
and CMDR has been written with START=1 and READ=0. START and SADR+W will then be
transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The
master polls the data line during this clock pulse and sets the Address Not Acknowledged bit
(ANAK

) in the Status Register if no slave acknowledges the address. 

After the address phase, the following is repeated:

while (NBYTES>0)

1.

Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY 
indicates the state of THR. Software or the Peripheral DMA Controller must write the 
data byte to THR.

2.

Transmit this data byte

3.

Decrement NBYTES

4.

If (NBYTES==0) and STOP=1, transmit STOP condition

Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data
bytes, ie START, SADR+W, STOP.

TWI transfers require the slave to acknowledge each received data byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not
acknowledge the data byte. As with the other status bits, an interrupt can be generated if
enabled in the Interrupt Enable Register (IER).

TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.

The end of a command is marked when the TWIM sets the SR.CCOMP bit. See 

 and

Figure 27-6. Master Write with One Data Byte

TWD

SR.IDLE

TXRDY

Write THR (DATA)

NBYTES set to 1

STOP sent automatically

(ACK received and NBYTES=0)

S

DADR

W

A

DATA

A

P